From: lkcl <lkcl@web>
Date: Fri, 1 Jan 2021 21:04:49 +0000 (+0000)
Subject: (no commit message)
X-Git-Tag: convert-csv-opcode-to-binary~657
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=141f70e90ff55e62641483796a867cd6b97e5a5f;p=libreriscv.git

---

diff --git a/openpower/sv/propagation.mdwn b/openpower/sv/propagation.mdwn
index fab0658ba..9cb9c56c2 100644
--- a/openpower/sv/propagation.mdwn
+++ b/openpower/sv/propagation.mdwn
@@ -4,3 +4,7 @@
 
 The basic principle is to have a special instruction in an svp64 context that takes a copy of the `RM[0..23]` bits, alongside a 16 bit suite of bits that indicates which of the following 16 32 bit instructions will have that `RM` applied to them.  
 
+| 0.5|6.10|11.15|16.31|  name   |
+| -- | -- | --- | --- | ------- |
+| OP | RT | RA  |     | I-Form  |
+| OP | RT | RA  | imm |         |