From: Jason Eckhardt <jle@rice.edu>
Date: Sat, 24 May 2003 04:22:23 +0000 (+0000)
Subject: 2003-05-23  Jason Eckhardt  <jle@rice.edu>
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=14218d5f2405e80541987be646c92af9c4bafa58;p=binutils-gdb.git

2003-05-23  Jason Eckhardt  <jle@rice.edu>
gas:
        * config/tc-i860.c (target_xp): Declare variable.
        (OPTION_XP): Declare macro.
        (md_longopts): Add option -mxp.
        (md_parse_option): Set target_xp.
        (md_show_usage): Add -mxp usage.
        (i860_process_insn): Recognize XP registers bear, ccr, p0-p3.
        (md_assemble): Don't try expansions if XP_ONLY is set.
        * doc/c-i860.texi: Document -mxp option.

gas/testsuite:
        * gas/i860/xp.s: New file.
        * gas/i860/xp.d: New file.

include/opcode:
        * i860.h (expand_type): Add XP_ONLY.
        (scyc.b): New XP instruction.
        (ldio.l): Likewise.
        (ldio.s): Likewise.
        (ldio.b): Likewise.
        (ldint.l): Likewise.
        (ldint.s): Likewise.
        (ldint.b): Likewise.
        (stio.l): Likewise.
        (stio.s): Likewise.
        (stio.b): Likewise.
        (pfld.q): Likewise.

opcodes:
        * i860-dis.c (crnames): Add bear, ccr, p0, p1, p2, p3.
        (print_insn_i860): Grab 4 bits of the control register field
        instead of 3.
---

diff --git a/gas/ChangeLog b/gas/ChangeLog
index 52e976a2d2b..f0bfd1a6c5b 100644
--- a/gas/ChangeLog
+++ b/gas/ChangeLog
@@ -1,3 +1,14 @@
+2003-05-23  Jason Eckhardt  <jle@rice.edu>
+
+	* config/tc-i860.c (target_xp): Declare variable.
+	(OPTION_XP): Declare macro.
+	(md_longopts): Add option -mxp.
+	(md_parse_option): Set target_xp.
+	(md_show_usage): Add -mxp usage.
+	(i860_process_insn): Recognize XP registers bear, ccr, p0-p3.
+	(md_assemble): Don't try expansions if XP_ONLY is set.
+	* doc/c-i860.texi: Document -mxp option and i860XP support.
+
 2003-05-23  Eric Christopher  <echristo@redhat.com>
 
 	* config/tc-mips.c (macro_build_jalr): Warning patrol.
diff --git a/gas/config/tc-i860.c b/gas/config/tc-i860.c
index cdb12cd58d9..3c6bc8e2788 100644
--- a/gas/config/tc-i860.c
+++ b/gas/config/tc-i860.c
@@ -1,5 +1,5 @@
 /* tc-i860.c -- Assembler for the Intel i860 architecture.
-   Copyright 1989, 1992, 1993, 1994, 1995, 1998, 1999, 2000, 2001, 2002
+   Copyright 1989, 1992, 1993, 1994, 1995, 1998, 1999, 2000, 2001, 2002, 2003
    Free Software Foundation, Inc.
 
    Brought back from the dead and completely reworked
@@ -88,6 +88,9 @@ static char last_expand;
 /* If true, then warn if any pseudo operations were expanded.  */
 static int target_warn_expand = 0;
 
+/* If true, then XP support is enabled.  */
+static int target_xp = 0;
+
 /* Prototypes.  */
 static void i860_process_insn	PARAMS ((char *));
 static void s_dual		PARAMS ((int));
@@ -229,7 +232,7 @@ md_assemble (str)
 
   /* Check for expandable flag to produce pseudo-instructions.  This
      is an undesirable feature that should be avoided.  */
-  if (the_insn.expand != 0
+  if (the_insn.expand != 0 && the_insn.expand != XP_ONLY
       && ! (the_insn.fi[0].fup & (OP_SEL_HA | OP_SEL_H | OP_SEL_L | OP_SEL_GOT
 			    | OP_SEL_GOTOFF | OP_SEL_PLT)))
     {
@@ -687,6 +690,43 @@ i860_process_insn (str)
 		  s += 4;
 		  continue;
 		}
+	      /* The remaining control registers are XP only.  */
+	      if (target_xp && strncmp (s, "bear", 4) == 0)
+		{
+		  opcode |= 0x6 << 21;
+		  s += 4;
+		  continue;
+		}
+	      if (target_xp && strncmp (s, "ccr", 3) == 0)
+		{
+		  opcode |= 0x7 << 21;
+		  s += 3;
+		  continue;
+		}
+	      if (target_xp && strncmp (s, "p0", 2) == 0)
+		{
+		  opcode |= 0x8 << 21;
+		  s += 2;
+		  continue;
+		}
+	      if (target_xp && strncmp (s, "p1", 2) == 0)
+		{
+		  opcode |= 0x9 << 21;
+		  s += 2;
+		  continue;
+		}
+	      if (target_xp && strncmp (s, "p2", 2) == 0)
+		{
+		  opcode |= 0xa << 21;
+		  s += 2;
+		  continue;
+		}
+	      if (target_xp && strncmp (s, "p3", 2) == 0)
+		{
+		  opcode |= 0xb << 21;
+		  s += 2;
+		  continue;
+		}
 	      break;
 
 	    /* 5-bit immediate in src1.  */
@@ -884,6 +924,10 @@ i860_process_insn (str)
     }
 
   the_insn.opcode = opcode;
+
+  /* Only recognize XP instructions when the user has requested it.  */
+  if (insn->expand == XP_ONLY && ! target_xp)
+    as_bad (_("Unknown opcode: `%s'"), insn->name);
 }
 
 static int
@@ -1030,11 +1074,13 @@ const char *md_shortopts = "";
 #define OPTION_EB		(OPTION_MD_BASE + 0)
 #define OPTION_EL		(OPTION_MD_BASE + 1)
 #define OPTION_WARN_EXPAND	(OPTION_MD_BASE + 2)
+#define OPTION_XP		(OPTION_MD_BASE + 3)
 
 struct option md_longopts[] = {
   { "EB",	    no_argument, NULL, OPTION_EB },
   { "EL",	    no_argument, NULL, OPTION_EL },
   { "mwarn-expand", no_argument, NULL, OPTION_WARN_EXPAND },
+  { "mxp",	    no_argument, NULL, OPTION_XP },
   { NULL,	    no_argument, NULL, 0 }
 };
 size_t md_longopts_size = sizeof (md_longopts);
@@ -1058,6 +1104,10 @@ md_parse_option (c, arg)
       target_warn_expand = 1;
       break;
 
+    case OPTION_XP:
+      target_xp = 1;
+      break;
+
 #ifdef OBJ_ELF
     /* SVR4 argument compatibility (-V): print version ID.  */
     case 'V':
@@ -1084,7 +1134,8 @@ md_show_usage (stream)
   fprintf (stream, _("\
   -EL			  generate code for little endian mode (default)\n\
   -EB			  generate code for big endian mode\n\
-  -mwarn-expand		  warn if pseudo operations are expanded\n"));
+  -mwarn-expand		  warn if pseudo operations are expanded\n\
+  -mxp			  enable i860XP support (disabled by default)\n"));
 #ifdef OBJ_ELF
   /* SVR4 compatibility flags.  */
   fprintf (stream, _("\
diff --git a/gas/doc/c-i860.texi b/gas/doc/c-i860.texi
index de01308bc84..01c89e7ca81 100644
--- a/gas/doc/c-i860.texi
+++ b/gas/doc/c-i860.texi
@@ -1,4 +1,4 @@
-@c Copyright 2000 Free Software Foundation, Inc.
+@c Copyright 2000, 2003 Free Software Foundation, Inc.
 @c This is part of the GAS manual.
 @c For copying conditions, see the file as.texinfo.
 @ifset GENERIC
@@ -62,6 +62,10 @@ will be expanded into two instructions. This is a very undesirable feature to
 rely on, so this flag can help detect any code where it happens. One
 use of it, for instance, has been to find and eliminate any place
 where @code{gcc} may emit these pseudo-instructions.
+@item -mxp
+Enable support for the i860XP instructions and control registers.  By default,
+this option is disabled so that only the base instruction set (i.e., i860XR)
+is supported.
 @end table
 
 @node Directives-i860
@@ -98,7 +102,7 @@ default register is @code{r31}.
 
 @cindex opcodes, i860
 @cindex i860 opcodes
-All of the Intel i860 machine instructions are supported. Please see
+All of the Intel i860XR and i860XP machine instructions are supported. Please see
 either @emph{i860 Microprocessor Programmer's Reference Manual} or @emph{i860 Microprocessor Architecture} for more information.
 @subsection Other instruction support (pseudo-instructions)
 For compatibility with some other i860 assemblers, a number of
diff --git a/gas/testsuite/ChangeLog b/gas/testsuite/ChangeLog
index b7541016cb8..ec0e1e8a35d 100644
--- a/gas/testsuite/ChangeLog
+++ b/gas/testsuite/ChangeLog
@@ -1,3 +1,8 @@
+2003-05-23  Jason Eckhardt  <jle@rice.edu>
+
+	* gas/i860/xp.s: New file.
+	* gas/i860/xp.d: New file.
+
 2003-05-23  Richard Earnshaw  <rearnsha@arm.com>
 
 	* gas/i860/i860.exp: Don't call exit if the target isn't an i860.
diff --git a/gas/testsuite/gas/i860/xp.d b/gas/testsuite/gas/i860/xp.d
new file mode 100644
index 00000000000..e9435a02583
--- /dev/null
+++ b/gas/testsuite/gas/i860/xp.d
@@ -0,0 +1,241 @@
+#as: -mxp
+#objdump: -dr
+#name: xp (XP-only instructions)
+
+.*: +file format .*
+
+Disassembly of section \.text:
+
+00000000 <\.text>:
+   0:	00 00 df 30 	ld.c	%bear,%r31
+   4:	00 00 c0 30 	ld.c	%bear,%r0
+   8:	00 00 e5 30 	ld.c	%ccr,%r5
+   c:	00 00 fe 30 	ld.c	%ccr,%r30
+  10:	00 00 0a 31 	ld.c	%p0,%r10
+  14:	00 00 02 31 	ld.c	%p0,%sp
+  18:	00 00 35 31 	ld.c	%p1,%r21
+  1c:	00 00 20 31 	ld.c	%p1,%r0
+  20:	00 00 5c 31 	ld.c	%p2,%r28
+  24:	00 00 4c 31 	ld.c	%p2,%r12
+  28:	00 00 7f 31 	ld.c	%p3,%r31
+  2c:	00 00 66 31 	ld.c	%p3,%r6
+  30:	00 00 c0 38 	st.c	%r0,%bear
+  34:	00 f0 c0 38 	st.c	%r30,%bear
+  38:	00 38 e0 38 	st.c	%r7,%ccr
+  3c:	00 f8 e0 38 	st.c	%r31,%ccr
+  40:	00 58 00 39 	st.c	%r11,%p0
+  44:	00 18 00 39 	st.c	%fp,%p0
+  48:	00 b0 20 39 	st.c	%r22,%p1
+  4c:	00 78 20 39 	st.c	%r15,%p1
+  50:	00 e8 40 39 	st.c	%r29,%p2
+  54:	00 68 40 39 	st.c	%r13,%p2
+  58:	00 20 60 39 	st.c	%r4,%p3
+  5c:	00 30 60 39 	st.c	%r6,%p3
+  60:	0a 04 05 4c 	ldint.l	%r0,%r5
+  64:	0a 04 df 4c 	ldint.l	%r6,%r31
+  68:	0a 04 fe 4c 	ldint.l	%r7,%r30
+  6c:	0a 04 1d 4d 	ldint.l	%r8,%r29
+  70:	0a 04 3c 4d 	ldint.l	%r9,%r28
+  74:	0a 04 1b 4c 	ldint.l	%r0,%r27
+  78:	0a 04 3a 4c 	ldint.l	%r1,%r26
+  7c:	0a 04 99 4d 	ldint.l	%r12,%r25
+  80:	0a 04 b8 4d 	ldint.l	%r13,%r24
+  84:	0a 04 d7 4d 	ldint.l	%r14,%r23
+  88:	0a 04 f6 4d 	ldint.l	%r15,%r22
+  8c:	0a 04 15 4e 	ldint.l	%r16,%r21
+  90:	0a 04 34 4e 	ldint.l	%r17,%r20
+  94:	0a 04 93 4f 	ldint.l	%r28,%r19
+  98:	0a 04 f2 4f 	ldint.l	%r31,%r18
+  9c:	0a 02 05 4c 	ldint.s	%r0,%r5
+  a0:	0a 02 df 4c 	ldint.s	%r6,%r31
+  a4:	0a 02 fe 4c 	ldint.s	%r7,%r30
+  a8:	0a 02 1d 4d 	ldint.s	%r8,%r29
+  ac:	0a 02 3c 4d 	ldint.s	%r9,%r28
+  b0:	0a 02 1b 4c 	ldint.s	%r0,%r27
+  b4:	0a 02 3a 4c 	ldint.s	%r1,%r26
+  b8:	0a 02 99 4d 	ldint.s	%r12,%r25
+  bc:	0a 02 b8 4d 	ldint.s	%r13,%r24
+  c0:	0a 02 d7 4d 	ldint.s	%r14,%r23
+  c4:	0a 02 f6 4d 	ldint.s	%r15,%r22
+  c8:	0a 02 15 4e 	ldint.s	%r16,%r21
+  cc:	0a 02 34 4e 	ldint.s	%r17,%r20
+  d0:	0a 02 93 4f 	ldint.s	%r28,%r19
+  d4:	0a 02 f2 4f 	ldint.s	%r31,%r18
+  d8:	0a 00 05 4c 	ldint.b	%r0,%r5
+  dc:	0a 00 df 4c 	ldint.b	%r6,%r31
+  e0:	0a 00 fe 4c 	ldint.b	%r7,%r30
+  e4:	0a 00 1d 4d 	ldint.b	%r8,%r29
+  e8:	0a 00 3c 4d 	ldint.b	%r9,%r28
+  ec:	0a 00 1b 4c 	ldint.b	%r0,%r27
+  f0:	0a 00 3a 4c 	ldint.b	%r1,%r26
+  f4:	0a 00 99 4d 	ldint.b	%r12,%r25
+  f8:	0a 00 b8 4d 	ldint.b	%r13,%r24
+  fc:	0a 00 d7 4d 	ldint.b	%r14,%r23
+ 100:	0a 00 f6 4d 	ldint.b	%r15,%r22
+ 104:	0a 00 15 4e 	ldint.b	%r16,%r21
+ 108:	0a 00 34 4e 	ldint.b	%r17,%r20
+ 10c:	0a 00 93 4f 	ldint.b	%r28,%r19
+ 110:	0a 00 f2 4f 	ldint.b	%r31,%r18
+ 114:	08 04 05 4c 	ldio.l	%r0,%r5
+ 118:	08 04 df 4c 	ldio.l	%r6,%r31
+ 11c:	08 04 fe 4c 	ldio.l	%r7,%r30
+ 120:	08 04 1d 4d 	ldio.l	%r8,%r29
+ 124:	08 04 3c 4d 	ldio.l	%r9,%r28
+ 128:	08 04 1b 4c 	ldio.l	%r0,%r27
+ 12c:	08 04 3a 4c 	ldio.l	%r1,%r26
+ 130:	08 04 99 4d 	ldio.l	%r12,%r25
+ 134:	08 04 b8 4d 	ldio.l	%r13,%r24
+ 138:	08 04 d7 4d 	ldio.l	%r14,%r23
+ 13c:	08 04 f6 4d 	ldio.l	%r15,%r22
+ 140:	08 04 15 4e 	ldio.l	%r16,%r21
+ 144:	08 04 34 4e 	ldio.l	%r17,%r20
+ 148:	08 04 93 4f 	ldio.l	%r28,%r19
+ 14c:	08 04 f2 4f 	ldio.l	%r31,%r18
+ 150:	08 02 05 4c 	ldio.s	%r0,%r5
+ 154:	08 02 df 4c 	ldio.s	%r6,%r31
+ 158:	08 02 fe 4c 	ldio.s	%r7,%r30
+ 15c:	08 02 1d 4d 	ldio.s	%r8,%r29
+ 160:	08 02 3c 4d 	ldio.s	%r9,%r28
+ 164:	08 02 1b 4c 	ldio.s	%r0,%r27
+ 168:	08 02 3a 4c 	ldio.s	%r1,%r26
+ 16c:	08 02 99 4d 	ldio.s	%r12,%r25
+ 170:	08 02 b8 4d 	ldio.s	%r13,%r24
+ 174:	08 02 d7 4d 	ldio.s	%r14,%r23
+ 178:	08 02 f6 4d 	ldio.s	%r15,%r22
+ 17c:	08 02 15 4e 	ldio.s	%r16,%r21
+ 180:	08 02 34 4e 	ldio.s	%r17,%r20
+ 184:	08 02 93 4f 	ldio.s	%r28,%r19
+ 188:	08 02 f2 4f 	ldio.s	%r31,%r18
+ 18c:	08 00 05 4c 	ldio.b	%r0,%r5
+ 190:	08 00 df 4c 	ldio.b	%r6,%r31
+ 194:	08 00 fe 4c 	ldio.b	%r7,%r30
+ 198:	08 00 1d 4d 	ldio.b	%r8,%r29
+ 19c:	08 00 3c 4d 	ldio.b	%r9,%r28
+ 1a0:	08 00 1b 4c 	ldio.b	%r0,%r27
+ 1a4:	08 00 3a 4c 	ldio.b	%r1,%r26
+ 1a8:	08 00 99 4d 	ldio.b	%r12,%r25
+ 1ac:	08 00 b8 4d 	ldio.b	%r13,%r24
+ 1b0:	08 00 d7 4d 	ldio.b	%r14,%r23
+ 1b4:	08 00 f6 4d 	ldio.b	%r15,%r22
+ 1b8:	08 00 15 4e 	ldio.b	%r16,%r21
+ 1bc:	08 00 34 4e 	ldio.b	%r17,%r20
+ 1c0:	08 00 93 4f 	ldio.b	%r28,%r19
+ 1c4:	08 00 f2 4f 	ldio.b	%r31,%r18
+ 1c8:	09 04 a0 4c 	stio.l	%r0,%r5
+ 1cc:	09 34 e0 4f 	stio.l	%r6,%r31
+ 1d0:	09 3c c0 4f 	stio.l	%r7,%r30
+ 1d4:	09 44 a0 4f 	stio.l	%r8,%r29
+ 1d8:	09 4c 80 4f 	stio.l	%r9,%r28
+ 1dc:	09 04 60 4f 	stio.l	%r0,%r27
+ 1e0:	09 0c 40 4f 	stio.l	%r1,%r26
+ 1e4:	09 64 20 4f 	stio.l	%r12,%r25
+ 1e8:	09 6c 00 4f 	stio.l	%r13,%r24
+ 1ec:	09 74 e0 4e 	stio.l	%r14,%r23
+ 1f0:	09 7c c0 4e 	stio.l	%r15,%r22
+ 1f4:	09 84 a0 4e 	stio.l	%r16,%r21
+ 1f8:	09 8c 80 4e 	stio.l	%r17,%r20
+ 1fc:	09 e4 60 4e 	stio.l	%r28,%r19
+ 200:	09 fc 40 4e 	stio.l	%r31,%r18
+ 204:	09 02 a0 4c 	stio.s	%r0,%r5
+ 208:	09 32 e0 4f 	stio.s	%r6,%r31
+ 20c:	09 3a c0 4f 	stio.s	%r7,%r30
+ 210:	09 42 a0 4f 	stio.s	%r8,%r29
+ 214:	09 4a 80 4f 	stio.s	%r9,%r28
+ 218:	09 02 60 4f 	stio.s	%r0,%r27
+ 21c:	09 0a 40 4f 	stio.s	%r1,%r26
+ 220:	09 62 20 4f 	stio.s	%r12,%r25
+ 224:	09 6a 00 4f 	stio.s	%r13,%r24
+ 228:	09 72 e0 4e 	stio.s	%r14,%r23
+ 22c:	09 7a c0 4e 	stio.s	%r15,%r22
+ 230:	09 82 a0 4e 	stio.s	%r16,%r21
+ 234:	09 8a 80 4e 	stio.s	%r17,%r20
+ 238:	09 e2 60 4e 	stio.s	%r28,%r19
+ 23c:	09 fa 40 4e 	stio.s	%r31,%r18
+ 240:	09 00 a0 4c 	stio.b	%r0,%r5
+ 244:	09 30 e0 4f 	stio.b	%r6,%r31
+ 248:	09 38 c0 4f 	stio.b	%r7,%r30
+ 24c:	09 40 a0 4f 	stio.b	%r8,%r29
+ 250:	09 48 80 4f 	stio.b	%r9,%r28
+ 254:	09 00 60 4f 	stio.b	%r0,%r27
+ 258:	09 08 40 4f 	stio.b	%r1,%r26
+ 25c:	09 60 20 4f 	stio.b	%r12,%r25
+ 260:	09 68 00 4f 	stio.b	%r13,%r24
+ 264:	09 70 e0 4e 	stio.b	%r14,%r23
+ 268:	09 78 c0 4e 	stio.b	%r15,%r22
+ 26c:	09 80 a0 4e 	stio.b	%r16,%r21
+ 270:	09 88 80 4e 	stio.b	%r17,%r20
+ 274:	09 e0 60 4e 	stio.b	%r28,%r19
+ 278:	09 f8 40 4e 	stio.b	%r31,%r18
+ 27c:	0b 00 00 4c 	scyc.b	%r0
+ 280:	0b 00 a0 4c 	scyc.b	%r5
+ 284:	0b 00 c0 4c 	scyc.b	%r6
+ 288:	0b 00 a0 4d 	scyc.b	%r13
+ 28c:	0b 00 c0 4d 	scyc.b	%r14
+ 290:	0b 00 80 4f 	scyc.b	%r28
+ 294:	0b 00 a0 4f 	scyc.b	%r29
+ 298:	0b 00 c0 4f 	scyc.b	%r30
+ 29c:	0b 00 e0 4f 	scyc.b	%r31
+ 2a0:	04 00 00 64 	pfld.q	0\(%r0\),%f0
+ 2a4:	84 00 3c 64 	pfld.q	128\(%r1\),%f28
+ 2a8:	04 01 58 64 	pfld.q	256\(%sp\),%f24
+ 2ac:	04 02 74 64 	pfld.q	512\(%fp\),%f20
+ 2b0:	04 04 90 64 	pfld.q	1024\(%r4\),%f16
+ 2b4:	04 10 ac 64 	pfld.q	4096\(%r5\),%f12
+ 2b8:	04 20 c8 64 	pfld.q	8192\(%r6\),%f8
+ 2bc:	04 40 e4 64 	pfld.q	16384\(%r7\),%f4
+ 2c0:	fc 7f e0 64 	pfld.q	32760\(%r7\),%f0
+ 2c4:	04 80 fc 64 	pfld.q	-32768\(%r7\),%f28
+ 2c8:	04 c0 18 65 	pfld.q	-16384\(%r8\),%f24
+ 2cc:	04 e0 34 65 	pfld.q	-8192\(%r9\),%f20
+ 2d0:	04 f0 50 65 	pfld.q	-4096\(%r10\),%f16
+ 2d4:	04 fc 6c 65 	pfld.q	-1024\(%r11\),%f12
+ 2d8:	04 fe 88 65 	pfld.q	-512\(%r12\),%f8
+ 2dc:	0c ff a4 65 	pfld.q	-248\(%r13\),%f4
+ 2e0:	fc ff c0 65 	pfld.q	-8\(%r14\),%f0
+ 2e4:	05 00 00 64 	pfld.q	0\(%r0\)\+\+,%f0
+ 2e8:	85 00 24 64 	pfld.q	128\(%r1\)\+\+,%f4
+ 2ec:	05 01 48 64 	pfld.q	256\(%sp\)\+\+,%f8
+ 2f0:	05 02 6c 64 	pfld.q	512\(%fp\)\+\+,%f12
+ 2f4:	05 04 90 64 	pfld.q	1024\(%r4\)\+\+,%f16
+ 2f8:	05 10 b4 64 	pfld.q	4096\(%r5\)\+\+,%f20
+ 2fc:	05 20 d8 64 	pfld.q	8192\(%r6\)\+\+,%f24
+ 300:	05 40 fc 64 	pfld.q	16384\(%r7\)\+\+,%f28
+ 304:	fd 7f e0 64 	pfld.q	32760\(%r7\)\+\+,%f0
+ 308:	05 80 e4 64 	pfld.q	-32768\(%r7\)\+\+,%f4
+ 30c:	05 c0 08 65 	pfld.q	-16384\(%r8\)\+\+,%f8
+ 310:	05 e0 2c 65 	pfld.q	-8192\(%r9\)\+\+,%f12
+ 314:	05 f0 50 65 	pfld.q	-4096\(%r10\)\+\+,%f16
+ 318:	05 fc 74 65 	pfld.q	-1024\(%r11\)\+\+,%f20
+ 31c:	05 fe 98 65 	pfld.q	-512\(%r12\)\+\+,%f24
+ 320:	0d ff bc 65 	pfld.q	-248\(%r13\)\+\+,%f28
+ 324:	fd ff d0 65 	pfld.q	-8\(%r14\)\+\+,%f16
+ 328:	04 28 1c 60 	pfld.q	%r5\(%r0\),%f28
+ 32c:	04 30 38 60 	pfld.q	%r6\(%r1\),%f24
+ 330:	04 38 54 60 	pfld.q	%r7\(%sp\),%f20
+ 334:	04 40 70 60 	pfld.q	%r8\(%fp\),%f16
+ 338:	04 48 8c 60 	pfld.q	%r9\(%r4\),%f12
+ 33c:	04 00 a8 60 	pfld.q	%r0\(%r5\),%f8
+ 340:	04 08 c4 60 	pfld.q	%r1\(%r6\),%f4
+ 344:	04 60 e0 60 	pfld.q	%r12\(%r7\),%f0
+ 348:	04 68 1c 61 	pfld.q	%r13\(%r8\),%f28
+ 34c:	04 70 38 61 	pfld.q	%r14\(%r9\),%f24
+ 350:	04 78 54 61 	pfld.q	%r15\(%r10\),%f20
+ 354:	04 80 70 61 	pfld.q	%r16\(%r11\),%f16
+ 358:	04 88 8c 61 	pfld.q	%r17\(%r12\),%f12
+ 35c:	04 e0 a8 61 	pfld.q	%r28\(%r13\),%f8
+ 360:	04 f8 c4 61 	pfld.q	%r31\(%r14\),%f4
+ 364:	05 28 00 60 	pfld.q	%r5\(%r0\)\+\+,%f0
+ 368:	05 30 24 60 	pfld.q	%r6\(%r1\)\+\+,%f4
+ 36c:	05 38 48 60 	pfld.q	%r7\(%sp\)\+\+,%f8
+ 370:	05 40 6c 60 	pfld.q	%r8\(%fp\)\+\+,%f12
+ 374:	05 48 90 60 	pfld.q	%r9\(%r4\)\+\+,%f16
+ 378:	05 00 b4 60 	pfld.q	%r0\(%r5\)\+\+,%f20
+ 37c:	05 08 d8 60 	pfld.q	%r1\(%r6\)\+\+,%f24
+ 380:	05 60 fc 60 	pfld.q	%r12\(%r7\)\+\+,%f28
+ 384:	05 68 00 61 	pfld.q	%r13\(%r8\)\+\+,%f0
+ 388:	05 70 24 61 	pfld.q	%r14\(%r9\)\+\+,%f4
+ 38c:	05 78 48 61 	pfld.q	%r15\(%r10\)\+\+,%f8
+ 390:	05 80 6c 61 	pfld.q	%r16\(%r11\)\+\+,%f12
+ 394:	05 88 90 61 	pfld.q	%r17\(%r12\)\+\+,%f16
+ 398:	05 e0 b4 61 	pfld.q	%r28\(%r13\)\+\+,%f20
+ 39c:	05 f8 d8 61 	pfld.q	%r31\(%r14\)\+\+,%f24
diff --git a/gas/testsuite/gas/i860/xp.s b/gas/testsuite/gas/i860/xp.s
new file mode 100644
index 00000000000..406c8f0fe05
--- /dev/null
+++ b/gas/testsuite/gas/i860/xp.s
@@ -0,0 +1,266 @@
+# This tests the XP-only instructions:
+#  ldint.x, ldio.x, stio.x, scyc.b, pfld.q
+# And control registers:
+#  %bear, %ccr, %p0, %p1, %p2, %p3
+
+	.text
+
+	# XP-only control registers
+	ld.c	%bear,%r31
+	ld.c	%bear,%r0
+	ld.c	%ccr,%r5
+	ld.c	%ccr,%r30
+	ld.c	%p0,%r10
+	ld.c	%p0,%r2
+	ld.c	%p1,%r21
+	ld.c	%p1,%r0
+	ld.c	%p2,%r28
+	ld.c	%p2,%r12
+	ld.c	%p3,%r31
+	ld.c	%p3,%r6
+
+	st.c	%r0,%bear
+	st.c	%r30,%bear
+	st.c	%r7,%ccr
+	st.c	%r31,%ccr
+	st.c	%r11,%p0
+	st.c	%r3,%p0
+	st.c	%r22,%p1
+	st.c	%r15,%p1
+	st.c	%r29,%p2
+	st.c	%r13,%p2
+	st.c	%r4,%p3
+	st.c	%r6,%p3
+
+	# ldint.{s,b,l}
+	ldint.l	%r0,%r5
+	ldint.l	%r6,%r31
+	ldint.l	%r7,%r30
+	ldint.l	%r8,%r29
+	ldint.l	%r9,%r28
+	ldint.l	%r0,%r27
+	ldint.l	%r1,%r26
+	ldint.l	%r12,%r25
+	ldint.l	%r13,%r24
+	ldint.l	%r14,%r23
+	ldint.l	%r15,%r22
+	ldint.l	%r16,%r21
+	ldint.l	%r17,%r20
+	ldint.l	%r28,%r19
+	ldint.l	%r31,%r18
+
+	ldint.s	%r0,%r5
+	ldint.s	%r6,%r31
+	ldint.s	%r7,%r30
+	ldint.s	%r8,%r29
+	ldint.s	%r9,%r28
+	ldint.s	%r0,%r27
+	ldint.s	%r1,%r26
+	ldint.s	%r12,%r25
+	ldint.s	%r13,%r24
+	ldint.s	%r14,%r23
+	ldint.s	%r15,%r22
+	ldint.s	%r16,%r21
+	ldint.s	%r17,%r20
+	ldint.s	%r28,%r19
+	ldint.s	%r31,%r18
+
+	ldint.b	%r0,%r5
+	ldint.b	%r6,%r31
+	ldint.b	%r7,%r30
+	ldint.b	%r8,%r29
+	ldint.b	%r9,%r28
+	ldint.b	%r0,%r27
+	ldint.b	%r1,%r26
+	ldint.b	%r12,%r25
+	ldint.b	%r13,%r24
+	ldint.b	%r14,%r23
+	ldint.b	%r15,%r22
+	ldint.b	%r16,%r21
+	ldint.b	%r17,%r20
+	ldint.b	%r28,%r19
+	ldint.b	%r31,%r18
+
+	# ldio.{s,b,l}
+	ldio.l	%r0,%r5
+	ldio.l	%r6,%r31
+	ldio.l	%r7,%r30
+	ldio.l	%r8,%r29
+	ldio.l	%r9,%r28
+	ldio.l	%r0,%r27
+	ldio.l	%r1,%r26
+	ldio.l	%r12,%r25
+	ldio.l	%r13,%r24
+	ldio.l	%r14,%r23
+	ldio.l	%r15,%r22
+	ldio.l	%r16,%r21
+	ldio.l	%r17,%r20
+	ldio.l	%r28,%r19
+	ldio.l	%r31,%r18
+
+	ldio.s	%r0,%r5
+	ldio.s	%r6,%r31
+	ldio.s	%r7,%r30
+	ldio.s	%r8,%r29
+	ldio.s	%r9,%r28
+	ldio.s	%r0,%r27
+	ldio.s	%r1,%r26
+	ldio.s	%r12,%r25
+	ldio.s	%r13,%r24
+	ldio.s	%r14,%r23
+	ldio.s	%r15,%r22
+	ldio.s	%r16,%r21
+	ldio.s	%r17,%r20
+	ldio.s	%r28,%r19
+	ldio.s	%r31,%r18
+
+	ldio.b	%r0,%r5
+	ldio.b	%r6,%r31
+	ldio.b	%r7,%r30
+	ldio.b	%r8,%r29
+	ldio.b	%r9,%r28
+	ldio.b	%r0,%r27
+	ldio.b	%r1,%r26
+	ldio.b	%r12,%r25
+	ldio.b	%r13,%r24
+	ldio.b	%r14,%r23
+	ldio.b	%r15,%r22
+	ldio.b	%r16,%r21
+	ldio.b	%r17,%r20
+	ldio.b	%r28,%r19
+	ldio.b	%r31,%r18
+
+	# stio.{s,b,l}
+	stio.l	%r0,%r5
+	stio.l	%r6,%r31
+	stio.l	%r7,%r30
+	stio.l	%r8,%r29
+	stio.l	%r9,%r28
+	stio.l	%r0,%r27
+	stio.l	%r1,%r26
+	stio.l	%r12,%r25
+	stio.l	%r13,%r24
+	stio.l	%r14,%r23
+	stio.l	%r15,%r22
+	stio.l	%r16,%r21
+	stio.l	%r17,%r20
+	stio.l	%r28,%r19
+	stio.l	%r31,%r18
+
+	stio.s	%r0,%r5
+	stio.s	%r6,%r31
+	stio.s	%r7,%r30
+	stio.s	%r8,%r29
+	stio.s	%r9,%r28
+	stio.s	%r0,%r27
+	stio.s	%r1,%r26
+	stio.s	%r12,%r25
+	stio.s	%r13,%r24
+	stio.s	%r14,%r23
+	stio.s	%r15,%r22
+	stio.s	%r16,%r21
+	stio.s	%r17,%r20
+	stio.s	%r28,%r19
+	stio.s	%r31,%r18
+
+	stio.b	%r0,%r5
+	stio.b	%r6,%r31
+	stio.b	%r7,%r30
+	stio.b	%r8,%r29
+	stio.b	%r9,%r28
+	stio.b	%r0,%r27
+	stio.b	%r1,%r26
+	stio.b	%r12,%r25
+	stio.b	%r13,%r24
+	stio.b	%r14,%r23
+	stio.b	%r15,%r22
+	stio.b	%r16,%r21
+	stio.b	%r17,%r20
+	stio.b	%r28,%r19
+	stio.b	%r31,%r18
+
+	# scyc.b
+	scyc.b	%r0
+	scyc.b	%r5
+	scyc.b	%r6
+	scyc.b	%r13
+	scyc.b	%r14
+	scyc.b	%r28
+	scyc.b	%r29
+	scyc.b	%r30
+	scyc.b	%r31
+
+	# pfld.q
+	# Immediate form, no auto-increment.
+	pfld.q	0(%r0),%f0
+	pfld.q	128(%r1),%f28
+	pfld.q	256(%r2),%f24
+	pfld.q	512(%r3),%f20
+	pfld.q	1024(%r4),%f16
+	pfld.q	4096(%r5),%f12
+	pfld.q	8192(%r6),%f8
+	pfld.q	16384(%r7),%f4
+	pfld.q	32760(%r7),%f0
+	pfld.q	-32768(%r7),%f28
+	pfld.q	-16384(%r8),%f24
+	pfld.q	-8192(%r9),%f20
+	pfld.q	-4096(%r10),%f16
+	pfld.q	-1024(%r11),%f12
+	pfld.q	-512(%r12),%f8
+	pfld.q	-248(%r13),%f4
+	pfld.q	-8(%r14),%f0
+
+	# Immediate form, with auto-increment.
+	pfld.q	0(%r0)++,%f0
+	pfld.q	128(%r1)++,%f4
+	pfld.q	256(%r2)++,%f8
+	pfld.q	512(%r3)++,%f12
+	pfld.q	1024(%r4)++,%f16
+	pfld.q	4096(%r5)++,%f20
+	pfld.q	8192(%r6)++,%f24
+	pfld.q	16384(%r7)++,%f28
+	pfld.q	32760(%r7)++,%f0
+	pfld.q	-32768(%r7)++,%f4
+	pfld.q	-16384(%r8)++,%f8
+	pfld.q	-8192(%r9)++,%f12
+	pfld.q	-4096(%r10)++,%f16
+	pfld.q	-1024(%r11)++,%f20
+	pfld.q	-512(%r12)++,%f24
+	pfld.q	-248(%r13)++,%f28
+	pfld.q	-8(%r14)++,%f16
+
+	# Index form, no auto-increment.
+	pfld.q	%r5(%r0),%f28
+	pfld.q	%r6(%r1),%f24
+	pfld.q	%r7(%r2),%f20
+	pfld.q	%r8(%r3),%f16
+	pfld.q	%r9(%r4),%f12
+	pfld.q	%r0(%r5),%f8
+	pfld.q	%r1(%r6),%f4
+	pfld.q	%r12(%r7),%f0
+	pfld.q	%r13(%r8),%f28
+	pfld.q	%r14(%r9),%f24
+	pfld.q	%r15(%r10),%f20
+	pfld.q	%r16(%r11),%f16
+	pfld.q	%r17(%r12),%f12
+	pfld.q	%r28(%r13),%f8
+	pfld.q	%r31(%r14),%f4
+
+	# Index form, with auto-increment.
+	pfld.q	%r5(%r0)++,%f0
+	pfld.q	%r6(%r1)++,%f4
+	pfld.q	%r7(%r2)++,%f8
+	pfld.q	%r8(%r3)++,%f12
+	pfld.q	%r9(%r4)++,%f16
+	pfld.q	%r0(%r5)++,%f20
+	pfld.q	%r1(%r6)++,%f24
+	pfld.q	%r12(%r7)++,%f28
+	pfld.q	%r13(%r8)++,%f0
+	pfld.q	%r14(%r9)++,%f4
+	pfld.q	%r15(%r10)++,%f8
+	pfld.q	%r16(%r11)++,%f12
+	pfld.q	%r17(%r12)++,%f16
+	pfld.q	%r28(%r13)++,%f20
+	pfld.q	%r31(%r14)++,%f24
+
+
diff --git a/include/opcode/ChangeLog b/include/opcode/ChangeLog
index 48004d0b674..9514813354b 100644
--- a/include/opcode/ChangeLog
+++ b/include/opcode/ChangeLog
@@ -1,11 +1,26 @@
+2003-05-23  Jason Eckhardt  <jle@rice.edu>
+
+	* i860.h (expand_type): Add XP_ONLY.
+	(scyc.b): New XP instruction.
+	(ldio.l): Likewise.
+	(ldio.s): Likewise.
+	(ldio.b): Likewise.
+	(ldint.l): Likewise.
+	(ldint.s): Likewise.
+	(ldint.b): Likewise.
+	(stio.l): Likewise.
+	(stio.s): Likewise.
+	(stio.b): Likewise.
+	(pfld.q): Likewise.
+
 2003-05-20  Jason Eckhardt  <jle@rice.edu>
 
-	opcode/i860.h (flush): Set lower 3 bits properly and use 'L'
+	* i860.h (flush): Set lower 3 bits properly and use 'L'
 	for the immediate operand type instead of 'i'.
 
 2003-05-20  Jason Eckhardt  <jle@rice.edu>
 
-	opcode/i860.h (fzchks): Both S and R bits must be set.
+	* i860.h (fzchks): Both S and R bits must be set.
 	(pfzchks): Likewise.
 	(faddp): Likewise.
 	(pfaddp): Likewise.
diff --git a/include/opcode/i860.h b/include/opcode/i860.h
index 6fdcdba6ecc..6e2a683a499 100644
--- a/include/opcode/i860.h
+++ b/include/opcode/i860.h
@@ -40,7 +40,7 @@ struct i860_opcode
 
 enum expand_type
 {
-    E_MOV = 1, E_ADDR, E_U32, E_AND, E_S32, E_DELAY
+    E_MOV = 1, E_ADDR, E_U32, E_AND, E_S32, E_DELAY, XP_ONLY
 };
 
 
@@ -135,6 +135,10 @@ static const struct i860_opcode i860_opcodes[] =
 { "pfld.d",	0x64000000, 0x98000007, "L(2),g", E_ADDR },	/* pfld.d #const(isrc2),fdest */
 { "pfld.d",	0x60000001, 0x9c000006, "1(2)++,g", 0 },	/* pfld.d isrc1(isrc2)++,fdest */
 { "pfld.d",	0x64000001, 0x98000006, "L(2)++,g", E_ADDR },	/* pfld.d #const(isrc2)++,fdest */
+{ "pfld.q",	0x60000004, 0x9c000003, "1(2),g", XP_ONLY },	/* pfld.q isrc1(isrc2),fdest */
+{ "pfld.q",	0x64000004, 0x98000003, "L(2),g", XP_ONLY },	/* pfld.q #const(isrc2),fdest */
+{ "pfld.q",	0x60000005, 0x9c000002, "1(2)++,g", XP_ONLY },	/* pfld.q isrc1(isrc2)++,fdest */
+{ "pfld.q",	0x64000005, 0x98000002, "L(2)++,g", XP_ONLY },	/* pfld.q #const(isrc2)++,fdest */
 
 { "fst.l",	0x28000002, 0xd4000001, "g,1(2)", 0 },	/* fst.l fdest,isrc1(isrc2) */
 { "fst.l",	0x2c000002, 0xd0000001, "g,K(2)", E_ADDR },	/* fst.l fdest,#const(isrc2) */
@@ -204,6 +208,16 @@ static const struct i860_opcode i860_opcodes[] =
 { "calli",	0x4c000002, 0xb000001d, "1", E_DELAY },	/* calli isrc1ni */
 { "intovr",	0x4c000004, 0xb000001b, "", 0 },	/* intovr trap on integer overflow */
 { "unlock",	0x4c000007, 0xb0000018, "", 0 },	/* unlock clear BL in dirbase */
+{ "ldio.l",	0x4c000408, 0xb00003f7, "2,d", XP_ONLY },	/* ldio.l isrc2,idest */
+{ "ldio.s",	0x4c000208, 0xb00005f7, "2,d", XP_ONLY },	/* ldio.s isrc2,idest */
+{ "ldio.b",	0x4c000008, 0xb00007f7, "2,d", XP_ONLY },	/* ldio.b isrc2,idest */
+{ "stio.l",	0x4c000409, 0xb00003f6, "1,2", XP_ONLY },	/* stio.l isrc1ni,isrc2 */
+{ "stio.s",	0x4c000209, 0xb00005f6, "1,2", XP_ONLY },	/* stio.s isrc1ni,isrc2 */
+{ "stio.b",	0x4c000009, 0xb00007f6, "1,2", XP_ONLY },	/* stio.b isrc1ni,isrc2 */
+{ "ldint.l",	0x4c00040a, 0xb00003f5, "2,d", XP_ONLY },	/* ldint.l isrc2,idest */
+{ "ldint.s",	0x4c00020a, 0xb00005f5, "2,d", XP_ONLY },	/* ldint.s isrc2,idest */
+{ "ldint.b",	0x4c00000a, 0xb00007f5, "2,d", XP_ONLY },	/* ldint.b isrc2,idest */
+{ "scyc.b",	0x4c00000b, 0xb00007f4, "2", XP_ONLY },		/* scyc.b isrc2 */
 
 /* CTRL-Format Instructions */
 { "br",		0x68000000, 0x94000000, "l", E_DELAY },	/* br lbroff */
diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog
index de8f363dac5..cbdcc3cfa68 100644
--- a/opcodes/ChangeLog
+++ b/opcodes/ChangeLog
@@ -1,3 +1,9 @@
+2003-05-23  Jason Eckhardt  <jle@rice.edu>
+
+	* i860-dis.c (crnames): Add bear, ccr, p0, p1, p2, p3.
+	(print_insn_i860): Grab 4 bits of the control register field
+	instead of 3.
+
 2003-05-18  Jason Eckhardt  <jle@rice.edu>
 
 	* i860-dis.c (print_insn_i860): Instruction shrd has a dual bit,
diff --git a/opcodes/i860-dis.c b/opcodes/i860-dis.c
index 69a106d41ca..a3e87b0f552 100644
--- a/opcodes/i860-dis.c
+++ b/opcodes/i860-dis.c
@@ -1,5 +1,5 @@
 /* Disassembler for the i860.
-   Copyright 2000 Free Software Foundation, Inc.
+   Copyright 2000, 2003 Free Software Foundation, Inc.
 
    Contributed by Jason Eckhardt <jle@cygnus.com>.
 
@@ -37,9 +37,11 @@ static const char *const frnames[] =
   "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23",
   "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31"};
 
-/* Control/status register names (encoded as 0..5 in the instruction).  */
+/* Control/status register names (encoded as 0..11 in the instruction).
+   Registers bear, ccr, p0, p1, p2 and p3 are XP only.  */
 static const char *const crnames[] = 
- {"fir", "psr", "dirbase", "db", "fsr", "epsr", "", ""};
+ {"fir", "psr", "dirbase", "db", "fsr", "epsr", "bear", "ccr",
+  "p0", "p1", "p2", "p3", "--", "--", "--", "--" };
 
 
 /* Prototypes.  */
@@ -190,7 +192,7 @@ print_insn_i860 (memaddr, info)
 	    /* Control register.  */
 	    case 'c':
 	      (*info->fprintf_func) (info->stream, "%s%s", I860_REG_PREFIX,
-				     crnames[(insn >> 21) & 0x7]);
+				     crnames[(insn >> 21) & 0xf]);
 	      break;
 
 	    /* 16-bit immediate (sign extend, except for bitwise ops).  */