From: Eddie Hung <eddie@fpgeh.com>
Date: Wed, 29 May 2019 22:24:09 +0000 (-0700)
Subject: Fix abc_test024
X-Git-Tag: working-ls180~1208^2~245
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=1423384367d4fa31f09c6c7b69c1b89edc3dd066;p=yosys.git

Fix abc_test024
---

diff --git a/backends/aiger/xaiger.cc b/backends/aiger/xaiger.cc
index 2ffd460dd..bf696bfd6 100644
--- a/backends/aiger/xaiger.cc
+++ b/backends/aiger/xaiger.cc
@@ -152,10 +152,11 @@ struct XAigerWriter
 				undriven_bits.insert(bit);
 				unused_bits.insert(bit);
 
-				if (wire->port_input)
-					input_bits.insert(bit);
-				else if (keep)
+				if (wire->port_input || keep) {
+					if (bit != wirebit)
+						alias_map[bit] = wirebit;
 					input_bits.insert(wirebit);
+				}
 
 				if (wire->port_output || keep) {
 					if (bit != wirebit)
@@ -166,7 +167,7 @@ struct XAigerWriter
 		}
 
 		for (auto bit : input_bits)
-			undriven_bits.erase(bit);
+			undriven_bits.erase(sigmap(bit));
 
 		for (auto bit : output_bits)
 			if (!bit.wire->port_input)