From: Rafael Antognolli Date: Mon, 5 Mar 2018 16:52:35 +0000 (-0800) Subject: intel/blorp: Update clear color state buffer during fast clears. X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=14260e7c60d936e94905a06e51e4e61c1b37a1e6;p=mesa.git intel/blorp: Update clear color state buffer during fast clears. We always want to update the fast clear color during a fast clear on i965. On anv, we are doing that before a resolve, but by adding support to blorp, we can do a similar thing and update it during a fast clear instead. The goal is to remove some code from anv that does such update, and centralize everything in blorp, hopefully removing a lot of code duplication. It also allows us to have a similar behavior on gen < 9 and gen >= 10. v5: s/we/we are/ (Jordan) Signed-off-by: Rafael Antognolli Reviewed-by: Jason Ekstrand Reviewed-by: Jordan Justen --- diff --git a/src/intel/blorp/blorp_genX_exec.h b/src/intel/blorp/blorp_genX_exec.h index eb64eaff0c8..7851228d8dc 100644 --- a/src/intel/blorp/blorp_genX_exec.h +++ b/src/intel/blorp/blorp_genX_exec.h @@ -1643,6 +1643,51 @@ blorp_emit_gen8_hiz_op(struct blorp_batch *batch, } #endif +static void +blorp_update_clear_color(struct blorp_batch *batch, + const struct brw_blorp_surface_info *info, + enum isl_aux_op op) +{ + if (info->clear_color_addr.buffer && op == ISL_AUX_OP_FAST_CLEAR) { +#if GEN_GEN >= 9 + for (int i = 0; i < 4; i++) { + blorp_emit(batch, GENX(MI_STORE_DATA_IMM), sdi) { + sdi.Address = info->clear_color_addr; + sdi.Address.offset += i * 4; + sdi.ImmediateData = info->clear_color.u32[i]; + } + } +#elif GEN_GEN >= 7 + blorp_emit(batch, GENX(MI_STORE_DATA_IMM), sdi) { + sdi.Address = info->clear_color_addr; + sdi.ImmediateData = ISL_CHANNEL_SELECT_RED << 25 | + ISL_CHANNEL_SELECT_GREEN << 22 | + ISL_CHANNEL_SELECT_BLUE << 19 | + ISL_CHANNEL_SELECT_ALPHA << 16; + if (isl_format_has_int_channel(info->view.format)) { + for (unsigned i = 0; i < 4; i++) { + assert(info->clear_color.u32[i] == 0 || + info->clear_color.u32[i] == 1); + } + sdi.ImmediateData |= (info->clear_color.u32[0] != 0) << 31; + sdi.ImmediateData |= (info->clear_color.u32[1] != 0) << 30; + sdi.ImmediateData |= (info->clear_color.u32[2] != 0) << 29; + sdi.ImmediateData |= (info->clear_color.u32[3] != 0) << 28; + } else { + for (unsigned i = 0; i < 4; i++) { + assert(info->clear_color.f32[i] == 0.0f || + info->clear_color.f32[i] == 1.0f); + } + sdi.ImmediateData |= (info->clear_color.f32[0] != 0.0f) << 31; + sdi.ImmediateData |= (info->clear_color.f32[1] != 0.0f) << 30; + sdi.ImmediateData |= (info->clear_color.f32[2] != 0.0f) << 29; + sdi.ImmediateData |= (info->clear_color.f32[3] != 0.0f) << 28; + } + } +#endif + } +} + /** * \brief Execute a blit or render pass operation. * @@ -1655,6 +1700,9 @@ blorp_emit_gen8_hiz_op(struct blorp_batch *batch, static void blorp_exec(struct blorp_batch *batch, const struct blorp_params *params) { + blorp_update_clear_color(batch, ¶ms->dst, params->fast_clear_op); + blorp_update_clear_color(batch, ¶ms->depth, params->hiz_op); + #if GEN_GEN >= 8 if (params->hiz_op != ISL_AUX_OP_NONE) { blorp_emit_gen8_hiz_op(batch, params);