From: Dmitry Selyutin Date: Tue, 16 Jan 2024 19:09:45 +0000 (+0300) Subject: oppc/code: refactor binary and unary exprs X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=142d6c47989c756ff4b0d3a2ea0aee1510199594;p=openpower-isa.git oppc/code: refactor binary and unary exprs --- diff --git a/src/openpower/oppc/pc_code.py b/src/openpower/oppc/pc_code.py index f6d7b908..df5fa319 100644 --- a/src/openpower/oppc/pc_code.py +++ b/src/openpower/oppc/pc_code.py @@ -269,7 +269,28 @@ class CodeVisitor(pc_util.Visitor): transient = self.transient(bits="UINT8_C(1)") else: transient = self.transient() - call = self.call(name=str(self[node.op]), code=[ + calls = { + pc_ast.Add: "oppc_add", + pc_ast.Sub: "oppc_sub", + pc_ast.Mul: "oppc_mul", + pc_ast.Div: "oppc_div", + pc_ast.Mod: "oppc_mod", + pc_ast.Lt: "oppc_lt", + pc_ast.Le: "oppc_le", + pc_ast.Eq: "oppc_eq", + pc_ast.Ne: "oppc_ne", + pc_ast.LtU: "oppc_ltu", + pc_ast.GtU: "oppc_gtu", + pc_ast.Ge: "oppc_ge", + pc_ast.Gt: "oppc_gt", + pc_ast.LShift: "oppc_lshift", + pc_ast.RShift: "oppc_rshift", + pc_ast.BitAnd: "oppc_and", + pc_ast.BitOr: "oppc_or", + pc_ast.BitXor: "oppc_xor", + pc_ast.BitConcat: "oppc_concat", + } + call = self.call(name=calls[node.op.__class__], code=[ self[transient], self[node.left], self[node.right], @@ -283,8 +304,13 @@ class CodeVisitor(pc_util.Visitor): yield node if isinstance(node.value, pc_ast.IfExpr): self.fixup_ternary(node=node.value) + calls = { + pc_ast.Not: "oppc_not", + pc_ast.Add: "oppc_plus", + pc_ast.Sub: "oppc_minus", + } transient = self.transient() - call = self.call(name=str(self[node.op]), code=[ + call = self.call(name=calls[node.op.__class__], code=[ self[transient], self[node.value], ]) @@ -305,29 +331,6 @@ class CodeVisitor(pc_util.Visitor): ) def Op(self, node): yield node - op = { - pc_ast.Not: "oppc_not", - pc_ast.Add: "oppc_add", - pc_ast.Sub: "oppc_sub", - pc_ast.Mul: "oppc_mul", - pc_ast.Div: "oppc_div", - pc_ast.Mod: "oppc_mod", - pc_ast.Lt: "oppc_lt", - pc_ast.Le: "oppc_le", - pc_ast.Eq: "oppc_eq", - pc_ast.Ne: "oppc_ne", - pc_ast.LtU: "oppc_ltu", - pc_ast.GtU: "oppc_gtu", - pc_ast.Ge: "oppc_ge", - pc_ast.Gt: "oppc_gt", - pc_ast.LShift: "oppc_lshift", - pc_ast.RShift: "oppc_rshift", - pc_ast.BitAnd: "oppc_and", - pc_ast.BitOr: "oppc_or", - pc_ast.BitXor: "oppc_xor", - pc_ast.BitConcat: "oppc_concat", - }[node.__class__] - self[node].emit(stmt=op) @pc_util.Hook(pc_ast.StringLiteral) def StringLiteral(self, node):