From: Miodrag Milanovic <mmicko@gmail.com>
Date: Fri, 4 Oct 2019 08:55:13 +0000 (+0200)
Subject: remove alu test
X-Git-Tag: working-ls180~988^2~7
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=1435b9bf97bc5c4e625bd3ef5db19065a0af2632;p=yosys.git

remove alu test
---

diff --git a/tests/anlogic/alu.v b/tests/anlogic/alu.v
deleted file mode 100644
index f82cc2e21..000000000
--- a/tests/anlogic/alu.v
+++ /dev/null
@@ -1,19 +0,0 @@
-module top (
-	input clock,
-	input [31:0] dinA, dinB,
-	input [2:0] opcode,
-	output reg [31:0] dout
-);
-	always @(posedge clock) begin
-		case (opcode)
-		0: dout <= dinA + dinB;
-		1: dout <= dinA - dinB;
-		2: dout <= dinA >> dinB;
-		3: dout <= $signed(dinA) >>> dinB;
-		4: dout <= dinA << dinB;
-		5: dout <= dinA & dinB;
-		6: dout <= dinA | dinB;
-		7: dout <= dinA ^ dinB;
-		endcase
-	end
-endmodule
diff --git a/tests/anlogic/alu.ys b/tests/anlogic/alu.ys
deleted file mode 100644
index 532ce82d5..000000000
--- a/tests/anlogic/alu.ys
+++ /dev/null
@@ -1,17 +0,0 @@
-read_verilog alu.v
-hierarchy -top top
-proc
-flatten
-equiv_opt -assert -map +/anlogic/cells_sim.v synth_anlogic # equivalency check
-design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
-cd top # Constrain all select calls below inside the top module
-
-select -assert-count 66 t:AL_MAP_ADDER
-select -assert-count 32 t:AL_MAP_LUT1
-select -assert-count 23 t:AL_MAP_LUT2
-select -assert-count 61 t:AL_MAP_LUT3
-select -assert-count 209 t:AL_MAP_LUT4
-select -assert-count 100 t:AL_MAP_LUT5
-select -assert-count 79 t:AL_MAP_LUT6
-select -assert-count 32 t:AL_MAP_SEQ
-select -assert-none t:AL_MAP_ADDER t:AL_MAP_LUT1 t:AL_MAP_LUT2 t:AL_MAP_LUT3 t:AL_MAP_LUT4 t:AL_MAP_LUT5 t:AL_MAP_LUT6 t:AL_MAP_SEQ %% t:* %D