From: Eddie Hung <eddie@fpgeh.com>
Date: Thu, 26 Sep 2019 18:13:08 +0000 (-0700)
Subject: Missing an '&'
X-Git-Tag: working-ls180~1046
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=143f82def2030527a4fa92b7ba60b704aad08e53;p=yosys.git

Missing an '&'
---

diff --git a/techlibs/xilinx/synth_xilinx.cc b/techlibs/xilinx/synth_xilinx.cc
index 173841799..888b5ed7b 100644
--- a/techlibs/xilinx/synth_xilinx.cc
+++ b/techlibs/xilinx/synth_xilinx.cc
@@ -244,7 +244,7 @@ struct SynthXilinxPass : public ScriptPass
 		}
 		extra_args(args, argidx, design);
 
-		if (family != "xcup" && family != "xcu" && family != "xc7" && family != "xc6v" & family != "xc6s")
+		if (family != "xcup" && family != "xcu" && family != "xc7" && family != "xc6v" && family != "xc6s")
 			log_cmd_error("Invalid Xilinx -family setting: '%s'.\n", family.c_str());
 
 		if (widemux != 0 && widemux < 2)