From: Emily Brickey Date: Tue, 4 Aug 2020 19:21:18 +0000 (-0700) Subject: cpu: update port terminology X-Git-Tag: v20.1.0.0~225 X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=144701703968fa5f66e1436ae35bdfb77d43c370;p=gem5.git cpu: update port terminology Change-Id: I891e7a74683c1775c75a62454fcfdecb7511b7e9 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/32312 Maintainer: Jason Lowe-Power Tested-by: kokoro Reviewed-by: Bobby R. Bruce --- diff --git a/src/cpu/BaseCPU.py b/src/cpu/BaseCPU.py index 96e96fc71..ee6c6461d 100644 --- a/src/cpu/BaseCPU.py +++ b/src/cpu/BaseCPU.py @@ -175,8 +175,8 @@ class BaseCPU(ClockedObject): tracer = Param.InstTracer(default_tracer, "Instruction tracer") - icache_port = MasterPort("Instruction Port") - dcache_port = MasterPort("Data Port") + icache_port = RequestPort("Instruction Port") + dcache_port = RequestPort("Data Port") _cached_ports = ['icache_port', 'dcache_port'] if buildEnv['TARGET_ISA'] in ['x86', 'arm', 'riscv']: diff --git a/src/cpu/base.hh b/src/cpu/base.hh index a00e83dc7..5c0c709cd 100644 --- a/src/cpu/base.hh +++ b/src/cpu/base.hh @@ -162,7 +162,7 @@ class BaseCPU : public ClockedObject virtual PortProxy::SendFunctionalFunc getSendFunctional() { - auto port = dynamic_cast(&getDataPort()); + auto port = dynamic_cast(&getDataPort()); assert(port); return [port](PacketPtr pkt)->void { port->sendFunctional(pkt); }; } diff --git a/src/cpu/checker/cpu.cc b/src/cpu/checker/cpu.cc index d9d6d7efa..b016938c9 100644 --- a/src/cpu/checker/cpu.cc +++ b/src/cpu/checker/cpu.cc @@ -113,13 +113,13 @@ CheckerCPU::setSystem(System *system) } void -CheckerCPU::setIcachePort(MasterPort *icache_port) +CheckerCPU::setIcachePort(RequestPort *icache_port) { icachePort = icache_port; } void -CheckerCPU::setDcachePort(MasterPort *dcache_port) +CheckerCPU::setDcachePort(RequestPort *dcache_port) { dcachePort = dcache_port; } diff --git a/src/cpu/checker/cpu.hh b/src/cpu/checker/cpu.hh index 6bd702276..3c040648a 100644 --- a/src/cpu/checker/cpu.hh +++ b/src/cpu/checker/cpu.hh @@ -99,9 +99,9 @@ class CheckerCPU : public BaseCPU, public ExecContext void setSystem(System *system); - void setIcachePort(MasterPort *icache_port); + void setIcachePort(RequestPort *icache_port); - void setDcachePort(MasterPort *dcache_port); + void setDcachePort(RequestPort *dcache_port); Port & getDataPort() override @@ -127,8 +127,8 @@ class CheckerCPU : public BaseCPU, public ExecContext System *systemPtr; - MasterPort *icachePort; - MasterPort *dcachePort; + RequestPort *icachePort; + RequestPort *dcachePort; ThreadContext *tc; diff --git a/src/cpu/kvm/base.hh b/src/cpu/kvm/base.hh index eff7a3c26..e999499ca 100644 --- a/src/cpu/kvm/base.hh +++ b/src/cpu/kvm/base.hh @@ -572,15 +572,15 @@ class BaseKvmCPU : public BaseCPU /** - * KVM memory port. Uses default MasterPort behavior and provides an + * KVM memory port. Uses default RequestPort behavior and provides an * interface for KVM to transparently submit atomic or timing requests. */ - class KVMCpuPort : public MasterPort + class KVMCpuPort : public RequestPort { public: KVMCpuPort(const std::string &_name, BaseKvmCPU *_cpu) - : MasterPort(_name, _cpu), cpu(_cpu), activeMMIOReqs(0) + : RequestPort(_name, _cpu), cpu(_cpu), activeMMIOReqs(0) { } /** * Interface to send Atomic or Timing IO request. Assumes that the pkt diff --git a/src/cpu/minor/cpu.hh b/src/cpu/minor/cpu.hh index b8ca087f5..579a96b05 100644 --- a/src/cpu/minor/cpu.hh +++ b/src/cpu/minor/cpu.hh @@ -95,7 +95,7 @@ class MinorCPU : public BaseCPU public: /** Provide a non-protected base class for Minor's Ports as derived * classes are created by Fetch1 and Execute */ - class MinorCPUPort : public MasterPort + class MinorCPUPort : public RequestPort { public: /** The enclosing cpu */ @@ -103,7 +103,7 @@ class MinorCPU : public BaseCPU public: MinorCPUPort(const std::string& name_, MinorCPU &cpu_) - : MasterPort(name_, &cpu_), cpu(cpu_) + : RequestPort(name_, &cpu_), cpu(cpu_) { } }; diff --git a/src/cpu/o3/fetch.hh b/src/cpu/o3/fetch.hh index 9939a00c9..77c6336bd 100644 --- a/src/cpu/o3/fetch.hh +++ b/src/cpu/o3/fetch.hh @@ -87,7 +87,7 @@ class DefaultFetch /** * IcachePort class for instruction fetch. */ - class IcachePort : public MasterPort + class IcachePort : public RequestPort { protected: /** Pointer to fetch. */ @@ -96,7 +96,7 @@ class DefaultFetch public: /** Default constructor. */ IcachePort(DefaultFetch *_fetch, FullO3CPU* _cpu) - : MasterPort(_cpu->name() + ".icache_port", _cpu), fetch(_fetch) + : RequestPort(_cpu->name() + ".icache_port", _cpu), fetch(_fetch) { } protected: @@ -377,7 +377,7 @@ class DefaultFetch /** The decoder. */ TheISA::Decoder *decoder[Impl::MaxThreads]; - MasterPort &getInstPort() { return icachePort; } + RequestPort &getInstPort() { return icachePort; } private: DynInstPtr buildInst(ThreadID tid, StaticInstPtr staticInst, diff --git a/src/cpu/o3/lsq.hh b/src/cpu/o3/lsq.hh index 9fa7ed586..9ef3b0ce8 100644 --- a/src/cpu/o3/lsq.hh +++ b/src/cpu/o3/lsq.hh @@ -119,7 +119,7 @@ class LSQ /** * DcachePort class for the load/store queue. */ - class DcachePort : public MasterPort + class DcachePort : public RequestPort { protected: @@ -130,7 +130,7 @@ class LSQ public: /** Default constructor. */ DcachePort(LSQ *_lsq, FullO3CPU* _cpu) - : MasterPort(_cpu->name() + ".dcache_port", _cpu), lsq(_lsq), + : RequestPort(_cpu->name() + ".dcache_port", _cpu), lsq(_lsq), cpu(_cpu) { } @@ -1053,7 +1053,7 @@ class LSQ /** Another store port is in use */ void cachePortBusy(bool is_load); - MasterPort &getDataPort() { return dcachePort; } + RequestPort &getDataPort() { return dcachePort; } protected: /** D-cache is blocked */ diff --git a/src/cpu/o3/lsq_unit.hh b/src/cpu/o3/lsq_unit.hh index e0cb68b24..16dddfd18 100644 --- a/src/cpu/o3/lsq_unit.hh +++ b/src/cpu/o3/lsq_unit.hh @@ -238,7 +238,7 @@ class LSQUnit void regStats(); /** Sets the pointer to the dcache port. */ - void setDcachePort(MasterPort *dcache_port); + void setDcachePort(RequestPort *dcache_port); /** Perform sanity checks after a drain. */ void drainSanityCheck() const; @@ -398,7 +398,7 @@ class LSQUnit LSQ *lsq; /** Pointer to the dcache port. Used only for sending. */ - MasterPort *dcachePort; + RequestPort *dcachePort; /** Particularisation of the LSQSenderState to the LQ. */ class LQSenderState : public LSQSenderState diff --git a/src/cpu/o3/lsq_unit_impl.hh b/src/cpu/o3/lsq_unit_impl.hh index 7383c6f9f..c39f8943d 100644 --- a/src/cpu/o3/lsq_unit_impl.hh +++ b/src/cpu/o3/lsq_unit_impl.hh @@ -245,7 +245,7 @@ LSQUnit::regStats() template void -LSQUnit::setDcachePort(MasterPort *dcache_port) +LSQUnit::setDcachePort(RequestPort *dcache_port) { dcachePort = dcache_port; } diff --git a/src/cpu/simple/atomic.cc b/src/cpu/simple/atomic.cc index d7a914ae0..34be352d9 100644 --- a/src/cpu/simple/atomic.cc +++ b/src/cpu/simple/atomic.cc @@ -272,7 +272,7 @@ AtomicSimpleCPU::suspendContext(ThreadID thread_num) } Tick -AtomicSimpleCPU::sendPacket(MasterPort &port, const PacketPtr &pkt) +AtomicSimpleCPU::sendPacket(RequestPort &port, const PacketPtr &pkt) { return port.sendAtomic(pkt); } diff --git a/src/cpu/simple/atomic.hh b/src/cpu/simple/atomic.hh index 53fe0fca4..7333e1ff4 100644 --- a/src/cpu/simple/atomic.hh +++ b/src/cpu/simple/atomic.hh @@ -101,7 +101,7 @@ class AtomicSimpleCPU : public BaseSimpleCPU */ bool tryCompleteDrain(); - virtual Tick sendPacket(MasterPort &port, const PacketPtr &pkt); + virtual Tick sendPacket(RequestPort &port, const PacketPtr &pkt); /** * An AtomicCPUPort overrides the default behaviour of the @@ -109,13 +109,13 @@ class AtomicSimpleCPU : public BaseSimpleCPU * also provides an implementation for the purely virtual timing * functions and panics on either of these. */ - class AtomicCPUPort : public MasterPort + class AtomicCPUPort : public RequestPort { public: AtomicCPUPort(const std::string &_name, BaseSimpleCPU* _cpu) - : MasterPort(_name, _cpu) + : RequestPort(_name, _cpu) { } protected: diff --git a/src/cpu/simple/noncaching.cc b/src/cpu/simple/noncaching.cc index 2596d791c..34e1ce2a2 100644 --- a/src/cpu/simple/noncaching.cc +++ b/src/cpu/simple/noncaching.cc @@ -52,7 +52,7 @@ NonCachingSimpleCPU::verifyMemoryMode() const } Tick -NonCachingSimpleCPU::sendPacket(MasterPort &port, const PacketPtr &pkt) +NonCachingSimpleCPU::sendPacket(RequestPort &port, const PacketPtr &pkt) { if (system->isMemAddr(pkt->getAddr())) { system->getPhysMem().access(pkt); diff --git a/src/cpu/simple/noncaching.hh b/src/cpu/simple/noncaching.hh index bfedff5e6..f57fef2fe 100644 --- a/src/cpu/simple/noncaching.hh +++ b/src/cpu/simple/noncaching.hh @@ -53,7 +53,7 @@ class NonCachingSimpleCPU : public AtomicSimpleCPU void verifyMemoryMode() const override; protected: - Tick sendPacket(MasterPort &port, const PacketPtr &pkt) override; + Tick sendPacket(RequestPort &port, const PacketPtr &pkt) override; }; #endif // __CPU_SIMPLE_NONCACHING_HH__ diff --git a/src/cpu/simple/timing.hh b/src/cpu/simple/timing.hh index c8bd05e54..2bb0fe643 100644 --- a/src/cpu/simple/timing.hh +++ b/src/cpu/simple/timing.hh @@ -155,12 +155,12 @@ class TimingSimpleCPU : public BaseSimpleCPU * scheduling of handling of incoming packets in the following * cycle. */ - class TimingCPUPort : public MasterPort + class TimingCPUPort : public RequestPort { public: TimingCPUPort(const std::string& _name, TimingSimpleCPU* _cpu) - : MasterPort(_name, _cpu), cpu(_cpu), + : RequestPort(_name, _cpu), cpu(_cpu), retryRespEvent([this]{ sendRetryResp(); }, name()) { } diff --git a/src/cpu/testers/directedtest/InvalidateGenerator.cc b/src/cpu/testers/directedtest/InvalidateGenerator.cc index 9351d91c4..5640163fd 100644 --- a/src/cpu/testers/directedtest/InvalidateGenerator.cc +++ b/src/cpu/testers/directedtest/InvalidateGenerator.cc @@ -54,7 +54,7 @@ InvalidateGenerator::~InvalidateGenerator() bool InvalidateGenerator::initiate() { - MasterPort* port; + RequestPort* port; Request::Flags flags; PacketPtr pkt; Packet::Command cmd; diff --git a/src/cpu/testers/directedtest/RubyDirectedTester.cc b/src/cpu/testers/directedtest/RubyDirectedTester.cc index afe2b1447..2bed14b71 100644 --- a/src/cpu/testers/directedtest/RubyDirectedTester.cc +++ b/src/cpu/testers/directedtest/RubyDirectedTester.cc @@ -105,7 +105,7 @@ RubyDirectedTester::CpuPort::recvTimingResp(PacketPtr pkt) return true; } -MasterPort* +RequestPort* RubyDirectedTester::getCpuPort(int idx) { assert(idx >= 0 && idx < ports.size()); diff --git a/src/cpu/testers/directedtest/RubyDirectedTester.hh b/src/cpu/testers/directedtest/RubyDirectedTester.hh index f0c694e82..de3e154cf 100644 --- a/src/cpu/testers/directedtest/RubyDirectedTester.hh +++ b/src/cpu/testers/directedtest/RubyDirectedTester.hh @@ -47,7 +47,7 @@ class DirectedGenerator; class RubyDirectedTester : public ClockedObject { public: - class CpuPort : public MasterPort + class CpuPort : public RequestPort { private: RubyDirectedTester *tester; @@ -55,7 +55,7 @@ class RubyDirectedTester : public ClockedObject public: CpuPort(const std::string &_name, RubyDirectedTester *_tester, PortID _id) - : MasterPort(_name, _tester, _id), tester(_tester) + : RequestPort(_name, _tester, _id), tester(_tester) {} protected: @@ -71,7 +71,7 @@ class RubyDirectedTester : public ClockedObject Port &getPort(const std::string &if_name, PortID idx=InvalidPortID) override; - MasterPort* getCpuPort(int idx); + RequestPort* getCpuPort(int idx); void init() override; @@ -98,7 +98,7 @@ class RubyDirectedTester : public ClockedObject RubyDirectedTester& operator=(const RubyDirectedTester& obj); uint64_t m_requests_completed; - std::vector ports; + std::vector ports; uint64_t m_requests_to_complete; DirectedGenerator* generator; }; diff --git a/src/cpu/testers/directedtest/SeriesRequestGenerator.cc b/src/cpu/testers/directedtest/SeriesRequestGenerator.cc index e5b7656d9..562b7d590 100644 --- a/src/cpu/testers/directedtest/SeriesRequestGenerator.cc +++ b/src/cpu/testers/directedtest/SeriesRequestGenerator.cc @@ -55,7 +55,7 @@ SeriesRequestGenerator::initiate() DPRINTF(DirectedTest, "initiating request\n"); assert(m_status == SeriesRequestGeneratorStatus_Thinking); - MasterPort* port = m_directed_tester->getCpuPort(m_active_node); + RequestPort* port = m_directed_tester->getCpuPort(m_active_node); Request::Flags flags; diff --git a/src/cpu/testers/garnet_synthetic_traffic/GarnetSyntheticTraffic.hh b/src/cpu/testers/garnet_synthetic_traffic/GarnetSyntheticTraffic.hh index df10f1700..524a960cb 100644 --- a/src/cpu/testers/garnet_synthetic_traffic/GarnetSyntheticTraffic.hh +++ b/src/cpu/testers/garnet_synthetic_traffic/GarnetSyntheticTraffic.hh @@ -74,14 +74,14 @@ class GarnetSyntheticTraffic : public ClockedObject protected: EventFunctionWrapper tickEvent; - class CpuPort : public MasterPort + class CpuPort : public RequestPort { GarnetSyntheticTraffic *tester; public: CpuPort(const std::string &_name, GarnetSyntheticTraffic *_tester) - : MasterPort(_name, _tester), tester(_tester) + : RequestPort(_name, _tester), tester(_tester) { } protected: diff --git a/src/cpu/testers/garnet_synthetic_traffic/GarnetSyntheticTraffic.py b/src/cpu/testers/garnet_synthetic_traffic/GarnetSyntheticTraffic.py index 616cab458..8ad00b642 100644 --- a/src/cpu/testers/garnet_synthetic_traffic/GarnetSyntheticTraffic.py +++ b/src/cpu/testers/garnet_synthetic_traffic/GarnetSyntheticTraffic.py @@ -51,5 +51,5 @@ class GarnetSyntheticTraffic(ClockedObject): after decimal point") response_limit = Param.Cycles(5000000, "Cycles before exiting \ due to lack of progress") - test = MasterPort("Port to the memory system to test") + test = RequestPort("Port to the memory system to test") system = Param.System(Parent.any, "System we belong to") diff --git a/src/cpu/testers/memtest/MemTest.py b/src/cpu/testers/memtest/MemTest.py index 36bc92951..eebcd971b 100644 --- a/src/cpu/testers/memtest/MemTest.py +++ b/src/cpu/testers/memtest/MemTest.py @@ -64,7 +64,7 @@ class MemTest(ClockedObject): progress_check = Param.Cycles(5000000, "Cycles before exiting " \ "due to lack of progress") - port = MasterPort("Port to the memory system") + port = RequestPort("Port to the memory system") system = Param.System(Parent.any, "System this tester is part of") # Add the ability to supress error responses on functional diff --git a/src/cpu/testers/memtest/memtest.hh b/src/cpu/testers/memtest/memtest.hh index fa13c0a49..86b27a4ac 100644 --- a/src/cpu/testers/memtest/memtest.hh +++ b/src/cpu/testers/memtest/memtest.hh @@ -91,14 +91,14 @@ class MemTest : public ClockedObject EventFunctionWrapper noResponseEvent; - class CpuPort : public MasterPort + class CpuPort : public RequestPort { MemTest &memtest; public: CpuPort(const std::string &_name, MemTest &_memtest) - : MasterPort(_name, &_memtest), memtest(_memtest) + : RequestPort(_name, &_memtest), memtest(_memtest) { } protected: diff --git a/src/cpu/testers/rubytest/Check.cc b/src/cpu/testers/rubytest/Check.cc index 90e7b877e..e3732bf5e 100644 --- a/src/cpu/testers/rubytest/Check.cc +++ b/src/cpu/testers/rubytest/Check.cc @@ -84,7 +84,7 @@ Check::initiatePrefetch() DPRINTF(RubyTest, "initiating prefetch\n"); int index = random_mt.random(0, m_num_readers - 1); - MasterPort* port = m_tester_ptr->getReadableCpuPort(index); + RequestPort* port = m_tester_ptr->getReadableCpuPort(index); Request::Flags flags; flags.set(Request::PREFETCH); @@ -142,7 +142,7 @@ Check::initiateFlush() DPRINTF(RubyTest, "initiating Flush\n"); int index = random_mt.random(0, m_num_writers - 1); - MasterPort* port = m_tester_ptr->getWritableCpuPort(index); + RequestPort* port = m_tester_ptr->getWritableCpuPort(index); Request::Flags flags; @@ -172,7 +172,7 @@ Check::initiateAction() assert(m_status == TesterStatus_Idle); int index = random_mt.random(0, m_num_writers - 1); - MasterPort* port = m_tester_ptr->getWritableCpuPort(index); + RequestPort* port = m_tester_ptr->getWritableCpuPort(index); Request::Flags flags; @@ -233,7 +233,7 @@ Check::initiateCheck() assert(m_status == TesterStatus_Ready); int index = random_mt.random(0, m_num_readers - 1); - MasterPort* port = m_tester_ptr->getReadableCpuPort(index); + RequestPort* port = m_tester_ptr->getReadableCpuPort(index); Request::Flags flags; diff --git a/src/cpu/testers/rubytest/RubyTester.cc b/src/cpu/testers/rubytest/RubyTester.cc index 30af47586..8dfe99479 100644 --- a/src/cpu/testers/rubytest/RubyTester.cc +++ b/src/cpu/testers/rubytest/RubyTester.cc @@ -203,7 +203,7 @@ RubyTester::isInstDataCpuPort(int idx) (idx < (m_num_inst_only_ports + m_num_inst_data_ports))); } -MasterPort* +RequestPort* RubyTester::getReadableCpuPort(int idx) { assert(idx >= 0 && idx < readPorts.size()); @@ -211,7 +211,7 @@ RubyTester::getReadableCpuPort(int idx) return readPorts[idx]; } -MasterPort* +RequestPort* RubyTester::getWritableCpuPort(int idx) { assert(idx >= 0 && idx < writePorts.size()); diff --git a/src/cpu/testers/rubytest/RubyTester.hh b/src/cpu/testers/rubytest/RubyTester.hh index 4ac553b4c..e63729ab5 100644 --- a/src/cpu/testers/rubytest/RubyTester.hh +++ b/src/cpu/testers/rubytest/RubyTester.hh @@ -57,7 +57,7 @@ class RubyTester : public ClockedObject { public: - class CpuPort : public MasterPort + class CpuPort : public RequestPort { private: RubyTester *tester; @@ -73,7 +73,7 @@ class RubyTester : public ClockedObject CpuPort(const std::string &_name, RubyTester *_tester, PortID _id, PortID _index) - : MasterPort(_name, _tester, _id), tester(_tester), + : RequestPort(_name, _tester, _id), tester(_tester), globalIdx(_index) {} @@ -101,8 +101,8 @@ class RubyTester : public ClockedObject bool isInstOnlyCpuPort(int idx); bool isInstDataCpuPort(int idx); - MasterPort* getReadableCpuPort(int idx); - MasterPort* getWritableCpuPort(int idx); + RequestPort* getReadableCpuPort(int idx); + RequestPort* getWritableCpuPort(int idx); void init() override; @@ -137,8 +137,8 @@ class RubyTester : public ClockedObject int m_num_cpus; uint64_t m_checks_completed; - std::vector writePorts; - std::vector readPorts; + std::vector writePorts; + std::vector readPorts; uint64_t m_checks_to_complete; int m_deadlock_threshold; int m_num_writers; diff --git a/src/cpu/testers/traffic_gen/BaseTrafficGen.py b/src/cpu/testers/traffic_gen/BaseTrafficGen.py index 0dda4ecfe..ff50a19ba 100644 --- a/src/cpu/testers/traffic_gen/BaseTrafficGen.py +++ b/src/cpu/testers/traffic_gen/BaseTrafficGen.py @@ -57,7 +57,7 @@ class BaseTrafficGen(ClockedObject): cxx_header = "cpu/testers/traffic_gen/traffic_gen.hh" # Port used for sending requests and receiving responses - port = MasterPort("Master port") + port = RequestPort("Master port") # System used to determine the mode of the memory system system = Param.System(Parent.any, "System this generator is part of") diff --git a/src/cpu/testers/traffic_gen/base.hh b/src/cpu/testers/traffic_gen/base.hh index 5205c3af5..17b1aa1cf 100644 --- a/src/cpu/testers/traffic_gen/base.hh +++ b/src/cpu/testers/traffic_gen/base.hh @@ -124,12 +124,12 @@ class BaseTrafficGen : public ClockedObject /** Master port specialisation for the traffic generator */ - class TrafficGenPort : public MasterPort + class TrafficGenPort : public RequestPort { public: TrafficGenPort(const std::string& name, BaseTrafficGen& traffic_gen) - : MasterPort(name, &traffic_gen), trafficGen(traffic_gen) + : RequestPort(name, &traffic_gen), trafficGen(traffic_gen) { } protected: diff --git a/src/cpu/trace/trace_cpu.hh b/src/cpu/trace/trace_cpu.hh index 0781c19cb..cd292fbb0 100644 --- a/src/cpu/trace/trace_cpu.hh +++ b/src/cpu/trace/trace_cpu.hh @@ -221,12 +221,12 @@ class TraceCPU : public BaseCPU /** * IcachePort class that interfaces with L1 Instruction Cache. */ - class IcachePort : public MasterPort + class IcachePort : public RequestPort { public: /** Default constructor. */ IcachePort(TraceCPU* _cpu) - : MasterPort(_cpu->name() + ".icache_port", _cpu), + : RequestPort(_cpu->name() + ".icache_port", _cpu), owner(_cpu) { } @@ -261,13 +261,13 @@ class TraceCPU : public BaseCPU /** * DcachePort class that interfaces with L1 Data Cache. */ - class DcachePort : public MasterPort + class DcachePort : public RequestPort { public: /** Default constructor. */ DcachePort(TraceCPU* _cpu) - : MasterPort(_cpu->name() + ".dcache_port", _cpu), + : RequestPort(_cpu->name() + ".dcache_port", _cpu), owner(_cpu) { } @@ -423,7 +423,7 @@ class TraceCPU : public BaseCPU public: /* Constructor */ FixedRetryGen(TraceCPU& _owner, const std::string& _name, - MasterPort& _port, MasterID master_id, + RequestPort& _port, MasterID master_id, const std::string& trace_file) : owner(_owner), port(_port), @@ -501,7 +501,7 @@ class TraceCPU : public BaseCPU TraceCPU& owner; /** Reference of the port to be used to issue memory requests. */ - MasterPort& port; + RequestPort& port; /** MasterID used for the requests being sent. */ const MasterID masterID; @@ -847,7 +847,7 @@ class TraceCPU : public BaseCPU public: /* Constructor */ ElasticDataGen(TraceCPU& _owner, const std::string& _name, - MasterPort& _port, MasterID master_id, + RequestPort& _port, MasterID master_id, const std::string& trace_file, TraceCPUParams *params) : owner(_owner), port(_port), @@ -984,7 +984,7 @@ class TraceCPU : public BaseCPU TraceCPU& owner; /** Reference of the port to be used to issue memory requests. */ - MasterPort& port; + RequestPort& port; /** MasterID used for the requests being sent. */ const MasterID masterID;