From: Alan Hayward <alan.hayward@arm.com>
Date: Wed, 22 Aug 2018 08:17:24 +0000 (+0100)
Subject: Add AArch64 SVE to NEWS and GDB manual
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=1461bdac5c1034467d7095b6d109689e02d03987;p=binutils-gdb.git

Add AArch64 SVE to NEWS and GDB manual

gdb/
	* NEWS: Add SVE to 8.2 section.

gdb/doc/
	* doc/gdb.texinfo (AArch64 SVE): New subsubsection.
---

diff --git a/gdb/ChangeLog b/gdb/ChangeLog
index 96bf87b8a2b..cfb07519074 100644
--- a/gdb/ChangeLog
+++ b/gdb/ChangeLog
@@ -1,3 +1,7 @@
+2018-08-21  Alan Hayward  <alan.hayward@arm.com>
+
+	* NEWS: Add SVE to 8.2 section.
+
 2018-08-21  Pedro Alves  <palves@redhat.com>
 
 	* guile/scm-utils.c (gdbscm_parse_function_args_1): New, factored
diff --git a/gdb/NEWS b/gdb/NEWS
index 16d3d725897..bd03d72e9af 100644
--- a/gdb/NEWS
+++ b/gdb/NEWS
@@ -90,6 +90,9 @@ GNU/Linux/RISC-V		riscv*-*-linux*
 * C expressions can now use _Alignof, and C++ expressions can now use
   alignof.
 
+* Support for SVE on AArch64 Linux.  Note that GDB does not detect changes to
+  the vector length while the process is running.
+
 * New commands
 
 set debug fbsd-nat
diff --git a/gdb/doc/ChangeLog b/gdb/doc/ChangeLog
index 8688b7fdd93..b14e35f79df 100644
--- a/gdb/doc/ChangeLog
+++ b/gdb/doc/ChangeLog
@@ -1,3 +1,7 @@
+2018-08-21  Alan Hayward  <alan.hayward@arm.com>
+
+	* gdb.texinfo (AArch64 SVE): New subsubsection.
+
 2018-08-14  Jan Vrany  <jan.vrany@fit.cvut.cz>
 
 	* gdb.texinfo (GDB/MI Data Manipulation): Document
diff --git a/gdb/doc/gdb.texinfo b/gdb/doc/gdb.texinfo
index 433a2698a92..eb898f9b1fe 100644
--- a/gdb/doc/gdb.texinfo
+++ b/gdb/doc/gdb.texinfo
@@ -23451,6 +23451,22 @@ Show whether AArch64 debugging messages are displayed.
 
 @end table
 
+@subsubsection AArch64 SVE.
+@cindex AArch64 SVE.
+
+When @value{GDBN} is debugging the AArch64 architecture, if the Scalable Vector
+Extension (SVE) is present, then @value{GDBN} will provide the vector registers
+@code{$z0} through @code{$z31}, vector predicate registers @code{$p0} through
+@code{$p15}, and the @code{$ffr} register.  In addition, the pseudo register
+@code{$vg} will be provided.  This is the vector granule for the current thread
+and represents the number of 64-bit chunks in an SVE @code{z} register.
+
+If the vector length changes, then the @code{$vg} register will be updated,
+but the lengths of the @code{z} and @code{p} registers will not change.  This
+is a known limitation of @value{GDBN} and does not affect the execution of the
+target process.
+
+
 @node i386
 @subsection x86 Architecture-specific Issues