From: Luke Kenneth Casson Leighton Date: Wed, 29 Sep 2021 15:43:50 +0000 (+0100) Subject: unit test for PartitionedSignal.__Cat__ X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=146ba804be0b9058e4efea26b33eb805ea3e6869;p=ieee754fpu.git unit test for PartitionedSignal.__Cat__ decided also to change the mask to be the number of partition points (not waste one bit) --- diff --git a/src/ieee754/part/test/test_partsig.py b/src/ieee754/part/test/test_partsig.py index c8b4066a..387a2e9c 100644 --- a/src/ieee754/part/test/test_partsig.py +++ b/src/ieee754/part/test/test_partsig.py @@ -2,7 +2,7 @@ # SPDX-License-Identifier: LGPL-2.1-or-later # See Notices.txt for copyright information -from nmigen import Signal, Module, Elaboratable, Mux +from nmigen import Signal, Module, Elaboratable, Mux, Cat from nmigen.back.pysim import Simulator, Delay from nmigen.cli import rtlil @@ -137,6 +137,26 @@ class TestMuxMod(Elaboratable): return m +class TestCatMod(Elaboratable): + def __init__(self, width, partpoints): + self.partpoints = partpoints + self.a = PartitionedSignal(partpoints, width) + self.b = PartitionedSignal(partpoints, width*2) + self.cat_sel = Signal(len(partpoints)+1) + self.cat_out = Signal(width*3) + + def elaborate(self, platform): + m = Module() + comb = m.d.comb + self.a.set_module(m) + self.b.set_module(m) + #self.cat_sel.set_module(m) + + comb += self.cat_out.eq(Cat(self.a, self.b)) + + return m + + class TestAddMod(Elaboratable): def __init__(self, width, partpoints): self.partpoints = partpoints @@ -279,6 +299,111 @@ class TestMux(unittest.TestCase): sim.run() +class TestCat(unittest.TestCase): + def test(self): + width = 16 + part_mask = Signal(3) # divide into 4-bits + module = TestCatMod(width, part_mask) + + test_name = "part_sig_mux" + traces = [part_mask, + module.a.sig, + module.b.sig, + module.cat_out] + sim = create_simulator(module, traces, test_name) + + # annoying recursive import issue + from ieee754.part_cat.cat import get_runlengths + + def async_process(): + + def test_catop(msg_prefix, *maskbit_list): + # define lengths of a/b test input + alen, blen = 16, 32 + # pairs of test values a, b + for a, b in [(0x0000, 0x00000000), + (0xDCBA, 0x12345678), + (0xABCD, 0x01234567), + (0xFFFF, 0x0000), + (0x0000, 0x0000), + (0x1F1F, 0xF1F1F1F1), + (0x0000, 0xFFFFFFFF)]: + # convert to mask_list + mask_list = [] + for mb in maskbit_list: + v = 0 + for i in range(4): + if mb & (1 << i): + v |= 0xf << (i*4) + mask_list.append(v) + + # convert a and b to partitions + apart, bpart = [], [] + ajump, bjump = alen // 4, blen // 4 + for i in range(4): + apart.append((a >> (ajump*i) & ((1<> (bjump*i) & ((1< 0x{y:X} != 0x{outval:X}, masklist %s" + # print ((msg % str(maskbit_list)).format(locals())) + self.assertEqual(y, outval, msg % str(maskbit_list)) + + yield part_mask.eq(0) + yield from test_catop("16-bit", 0b1111) + yield part_mask.eq(0b10) + yield from test_catop("8-bit", 0b1100, 0b0011) + yield part_mask.eq(0b1111) + yield from test_catop("4-bit", 0b1000, 0b0100, 0b0010, 0b0001) + + sim.add_process(async_process) + with sim.write_vcd( + vcd_file=open(test_name + ".vcd", "w"), + gtkw_file=open(test_name + ".gtkw", "w"), + traces=traces): + sim.run() + + class TestPartitionedSignal(unittest.TestCase): def test(self): width = 16 diff --git a/src/ieee754/part_cat/cat.py b/src/ieee754/part_cat/cat.py index a9541080..6fdfb66b 100644 --- a/src/ieee754/part_cat/cat.py +++ b/src/ieee754/part_cat/cat.py @@ -73,6 +73,8 @@ class PartitionedCat(Elaboratable): """ # work out the length (total of all PartitionedSignals) self.catlist = catlist + if isinstance(mask, dict): + mask = list(mask.values()) self.mask = mask width = 0 for p in catlist: @@ -101,7 +103,8 @@ class PartitionedCat(Elaboratable): keys = list(self.partition_points.keys()) print ("keys", keys, "values", self.partition_points.values()) - with m.Switch(self.mask[:-1]): + print ("mask", self.mask) + with m.Switch(Cat(self.mask)): # for each partition possibility, create a Cat sequence for pbit in range(1<