From: Richard Sandiford Date: Tue, 5 Sep 2017 20:08:41 +0000 (+0000) Subject: [75/77] Use scalar_mode in the AArch64 port X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=146c2e3ad070b6ba29bd48865ebb5c909f27d8e6;p=gcc.git [75/77] Use scalar_mode in the AArch64 port Similar to the previous scalar_int_mode patch. 2017-09-05 Richard Sandiford Alan Hayward David Sherwood gcc/ * config/aarch64/aarch64-protos.h (aarch64_gen_adjusted_ldpstp): Take a scalar_mode rather than a machine_mode. (aarch64_operands_adjust_ok_for_ldpstp): Likewise. * config/aarch64/aarch64.c (aarch64_simd_container_mode): Likewise. (aarch64_operands_adjust_ok_for_ldpstp): Likewise. (aarch64_gen_adjusted_ldpstp): Likewise. (aarch64_expand_vector_init): Use scalar_mode instead of machine_mode. Co-Authored-By: Alan Hayward Co-Authored-By: David Sherwood From-SVN: r251736 --- diff --git a/gcc/ChangeLog b/gcc/ChangeLog index ae3edf516ab..3d38a7ae94c 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,15 @@ +2017-09-05 Richard Sandiford + Alan Hayward + David Sherwood + + * config/aarch64/aarch64-protos.h (aarch64_gen_adjusted_ldpstp): + Take a scalar_mode rather than a machine_mode. + (aarch64_operands_adjust_ok_for_ldpstp): Likewise. + * config/aarch64/aarch64.c (aarch64_simd_container_mode): Likewise. + (aarch64_operands_adjust_ok_for_ldpstp): Likewise. + (aarch64_gen_adjusted_ldpstp): Likewise. + (aarch64_expand_vector_init): Use scalar_mode instead of machine_mode. + 2017-09-05 Richard Sandiford Alan Hayward David Sherwood diff --git a/gcc/config/aarch64/aarch64-protos.h b/gcc/config/aarch64/aarch64-protos.h index d2164058de4..ed5d373dc10 100644 --- a/gcc/config/aarch64/aarch64-protos.h +++ b/gcc/config/aarch64/aarch64-protos.h @@ -441,7 +441,7 @@ bool aarch64_atomic_ldop_supported_p (enum rtx_code); void aarch64_gen_atomic_ldop (enum rtx_code, rtx, rtx, rtx, rtx, rtx); void aarch64_split_atomic_op (enum rtx_code, rtx, rtx, rtx, rtx, rtx, rtx); -bool aarch64_gen_adjusted_ldpstp (rtx *, bool, machine_mode, RTX_CODE); +bool aarch64_gen_adjusted_ldpstp (rtx *, bool, scalar_mode, RTX_CODE); #endif /* RTX_CODE */ void aarch64_init_builtins (void); @@ -469,7 +469,7 @@ int aarch64_ccmp_mode_to_code (machine_mode mode); bool extract_base_offset_in_addr (rtx mem, rtx *base, rtx *offset); bool aarch64_operands_ok_for_ldpstp (rtx *, bool, machine_mode); -bool aarch64_operands_adjust_ok_for_ldpstp (rtx *, bool, machine_mode); +bool aarch64_operands_adjust_ok_for_ldpstp (rtx *, bool, scalar_mode); extern void aarch64_asm_output_pool_epilogue (FILE *, const char *, tree, HOST_WIDE_INT); diff --git a/gcc/config/aarch64/aarch64.c b/gcc/config/aarch64/aarch64.c index 3d16a7ad5c3..a2ecd7ac336 100644 --- a/gcc/config/aarch64/aarch64.c +++ b/gcc/config/aarch64/aarch64.c @@ -149,7 +149,7 @@ static bool aarch64_builtin_support_vector_misalignment (machine_mode mode, int misalignment, bool is_packed); static machine_mode -aarch64_simd_container_mode (machine_mode mode, unsigned width); +aarch64_simd_container_mode (scalar_mode mode, unsigned width); /* Major revision number of the ARM Architecture implemented by the target. */ unsigned aarch64_architecture_version; @@ -11248,7 +11248,7 @@ aarch64_vector_mode_supported_p (machine_mode mode) /* Return appropriate SIMD container for MODE within a vector of WIDTH bits. */ static machine_mode -aarch64_simd_container_mode (machine_mode mode, unsigned width) +aarch64_simd_container_mode (scalar_mode mode, unsigned width) { gcc_assert (width == 64 || width == 128); if (TARGET_SIMD) @@ -11997,7 +11997,7 @@ void aarch64_expand_vector_init (rtx target, rtx vals) { machine_mode mode = GET_MODE (target); - machine_mode inner_mode = GET_MODE_INNER (mode); + scalar_mode inner_mode = GET_MODE_INNER (mode); /* The number of vector elements. */ int n_elts = GET_MODE_NUNITS (mode); /* The number of vector elements which are not constant. */ @@ -14810,7 +14810,7 @@ aarch64_operands_ok_for_ldpstp (rtx *operands, bool load, bool aarch64_operands_adjust_ok_for_ldpstp (rtx *operands, bool load, - machine_mode mode) + scalar_mode mode) { enum reg_class rclass_1, rclass_2, rclass_3, rclass_4; HOST_WIDE_INT offval_1, offval_2, offval_3, offval_4, msize; @@ -14944,7 +14944,7 @@ aarch64_operands_adjust_ok_for_ldpstp (rtx *operands, bool load, bool aarch64_gen_adjusted_ldpstp (rtx *operands, bool load, - machine_mode mode, RTX_CODE code) + scalar_mode mode, RTX_CODE code) { rtx base, offset, t1, t2; rtx mem_1, mem_2, mem_3, mem_4;