From: Florent Kermarrec <florent@enjoy-digital.fr>
Date: Wed, 8 Jul 2020 06:33:52 +0000 (+0200)
Subject: buid/io/InferedSDRIO/InferedSDRTristate: avoid unnecessary clk_domain/limitation.
X-Git-Tag: 24jan2021_ls180~94
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=146ead4c4c18e267ccef988c12d3348c5a283d90;p=litex.git

buid/io/InferedSDRIO/InferedSDRTristate: avoid unnecessary clk_domain/limitation.

Just create a local clk_domain from clk signal.
---

diff --git a/litex/build/io.py b/litex/build/io.py
index 42f9531e..8e93d19b 100644
--- a/litex/build/io.py
+++ b/litex/build/io.py
@@ -43,12 +43,10 @@ class DifferentialOutput(Special):
 # SDR Input/Output ---------------------------------------------------------------------------------
 
 class InferedSDRIO(Module):
-    def __init__(self, i, o, clk, clk_domain):
-        if clk_domain is None:
-            raise NotImplementedError("Attempted to use an InferedSDRIO but no clk_domain specified.")
-        sync = getattr(self.sync, clk_domain)
-        sync += o.eq(i)
-
+    def __init__(self, i, o, clk):
+        self.clock_domains.cd_sdrio = ClockDomain(reset_less=True)
+        self.comb += self.cd_sdrio.clk.eq(clk)
+        self.sync.sdrio += o.eq(i)
 
 class SDRIO(Special):
     def __init__(self, i, o, clk=ClockSignal()):
@@ -75,15 +73,13 @@ class SDROutput(SDRIO): pass
 # SDR Tristate -------------------------------------------------------------------------------------
 
 class InferedSDRTristate(Module):
-    def __init__(self, io, o, oe, i, clk, clk_domain):
-        if clk_domain is None:
-            raise NotImplementedError("Attempted to use an SDRTristate but no clk_domain specified.")
+    def __init__(self, io, o, oe, i, clk):
         _o  = Signal()
         _oe = Signal()
         _i  = Signal()
         self.specials += SDROutput(o, _o, clk)
         self.specials += SDRInput(_i, i, clk)
-        self.submodules += InferedSDRIO(oe, _oe, clk, clk_domain)
+        self.submodules += InferedSDRIO(oe, _oe, clk)
         self.specials += Tristate(io, _o, _oe, _i)
 
 class SDRTristate(Special):
@@ -95,7 +91,6 @@ class SDRTristate(Special):
         self.oe           = wrap(oe)
         self.i            = wrap(i)
         self.clk          = wrap(clk)
-        self.clk_domain   = None if not hasattr(clk, "cd") else clk.cd
 
     def iter_expressions(self):
         yield self, "io",  SPECIAL_INOUT
@@ -106,7 +101,7 @@ class SDRTristate(Special):
 
     @staticmethod
     def lower(dr):
-        return InferedSDRTristate(dr.io, dr.o, dr.oe, dr.i, dr.clk, dr.clk_domain)
+        return InferedSDRTristate(dr.io, dr.o, dr.oe, dr.i, dr.clk)
 
 # DDR Input/Output ---------------------------------------------------------------------------------