From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Wed, 22 May 2019 08:57:46 +0000 (+0100)
Subject: add extra regression test
X-Git-Tag: div_pipeline~1997
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=14764494e35a1e4ae312f70a7abc255f23611ce9;p=soc.git

add extra regression test
---

diff --git a/src/experiment/score6600.py b/src/experiment/score6600.py
index 455dfec5..5ba2861b 100644
--- a/src/experiment/score6600.py
+++ b/src/experiment/score6600.py
@@ -373,8 +373,8 @@ def scoreboard_sim(dut, alusim):
         alusim.setval(i, 4+i*2)
 
     instrs = []
-    if False:
-        for i in range(50):
+    if True:
+        for i in range(5):
             src1 = randint(1, dut.n_regs-1)
             src2 = randint(1, dut.n_regs-1)
             while True:
@@ -407,11 +407,10 @@ def scoreboard_sim(dut, alusim):
         instrs.append((2, 6, 2, 1))
         instrs.append((2, 1, 2, 0))
 
-    if True:
-        instrs.append((1, 4, 7, 1))
+    if False:
+        instrs.append((1, 2, 7, 1))
         instrs.append((7, 1, 5, 0))
-        instrs.append((4, 3, 1, 1))
-        instrs.append((6, 5, 7, 1))
+        instrs.append((4, 4, 1, 1))
 
     for i, (src1, src2, dest, op) in enumerate(instrs):
 
@@ -429,7 +428,6 @@ def scoreboard_sim(dut, alusim):
             yield from print_reg(dut, [1,2,3])
             yield
         yield from print_reg(dut, [1,2,3])
-        yield
 
     yield
     yield from print_reg(dut, [1,2,3])