From: Michael Nolan Date: Mon, 10 Feb 2020 14:42:34 +0000 (-0500) Subject: Add neg operator to partsig.py X-Git-Tag: ls180-24jan2020~207 X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=1480761db420032eb229e737658fcb6bed3aec99;p=ieee754fpu.git Add neg operator to partsig.py --- diff --git a/src/ieee754/part/partsig.py b/src/ieee754/part/partsig.py index a4cad8d6..833451db 100644 --- a/src/ieee754/part/partsig.py +++ b/src/ieee754/part/partsig.py @@ -61,8 +61,8 @@ class PartitionedSignal: # unary ops that require partitioning def __neg__(self): - # TODO use PartitionedAdder for this, with a "neg" mode? - return Operator("-", [self]) + result, _ = self.add_op(self, ~0, carry=0) # TODO, subop + return result # binary ops that don't require partitioning diff --git a/src/ieee754/part/test/test_partsig.py b/src/ieee754/part/test/test_partsig.py index ce8464c9..cc881be3 100644 --- a/src/ieee754/part/test/test_partsig.py +++ b/src/ieee754/part/test/test_partsig.py @@ -49,6 +49,7 @@ class TestAddMod(Elaboratable): self.carry_in = Signal(len(partpoints)+1) self.add_carry_out = Signal(len(partpoints)+1) self.sub_carry_out = Signal(len(partpoints)+1) + self.neg_output = Signal(width) def elaborate(self, platform): m = Module() @@ -71,6 +72,7 @@ class TestAddMod(Elaboratable): self.carry_in) m.d.comb += self.sub_output.eq(sub_out) m.d.comb += self.sub_carry_out.eq(add_carry) + m.d.comb += self.neg_output.eq(-self.a) ppts = self.partpoints m.d.comb += self.mux_out.eq(PMux(m, ppts, self.mux_sel, self.a, self.b)) @@ -100,6 +102,10 @@ class TestPartitionPoints(unittest.TestCase): lsb = mask & ~(mask-1) if carry_in else 0 return mask & ((a & mask) + (~b & mask) + lsb) + def test_neg_fn(carry_in, a, b, mask): + lsb = mask & ~(mask-1) if carry_in else 0 + return mask & ((a & mask) + (~0 & mask)) + def test_op(msg_prefix, carry, test_fn, mod_attr, *mask_list): rand_data = [] for i in range(100): @@ -129,6 +135,7 @@ class TestPartitionPoints(unittest.TestCase): for (test_fn, mod_attr) in ((test_add_fn, "add"), (test_sub_fn, "sub"), + (test_neg_fn, "neg"), ): yield part_mask.eq(0) yield from test_op("16-bit", 1, test_fn, mod_attr, 0xFFFF)