From: Luke Kenneth Casson Leighton Date: Wed, 8 May 2019 10:39:33 +0000 (+0100) Subject: make SR Latch async again, make busy signal sync into issue unit X-Git-Tag: div_pipeline~2103 X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=1488e769dd9d5cd81a3bbfccb6bce1a2af0f4e20;p=soc.git make SR Latch async again, make busy signal sync into issue unit --- diff --git a/src/experiment/cscore.py b/src/experiment/cscore.py index 5cc54540..e3f19c66 100644 --- a/src/experiment/cscore.py +++ b/src/experiment/cscore.py @@ -140,12 +140,12 @@ class Scoreboard(Elaboratable): for i, fu in enumerate(il): fn_issue_l.append(fu.issue_i) fn_busy_l.append(fu.busy_o) - # XXX sync, so as to stop a simulation infinite loop m.d.comb += fu.issue_i.eq(issueunit.i.fn_issue_o[i]) m.d.comb += fu.dest_i.eq(issueunit.i.dest_i) m.d.comb += fu.src1_i.eq(issueunit.i.src1_i) m.d.comb += fu.src2_i.eq(issueunit.i.src2_i) - m.d.comb += issueunit.i.busy_i[i].eq(fu.busy_o) + # XXX sync, so as to stop a simulation infinite loop + m.d.sync += issueunit.i.busy_i[i].eq(fu.busy_o) #--------- # connect Function Units diff --git a/src/scoreboard/fn_unit.py b/src/scoreboard/fn_unit.py index ba4e1929..a21911d3 100644 --- a/src/scoreboard/fn_unit.py +++ b/src/scoreboard/fn_unit.py @@ -79,7 +79,7 @@ class FnUnit(Elaboratable): def elaborate(self, platform): m = Module() m.submodules.rd_l = rd_l = SRLatch(sync=False) - m.submodules.wr_l = wr_l = SRLatch(sync=True) + m.submodules.wr_l = wr_l = SRLatch(sync=False) m.submodules.dest_d = dest_d = Decoder(self.reg_width) m.submodules.src1_d = src1_d = Decoder(self.reg_width) m.submodules.src2_d = src2_d = Decoder(self.reg_width)