From: Paul Berry Date: Thu, 19 Jul 2012 14:58:30 +0000 (-0700) Subject: i965: Use sendc for all render target writes on Gen6+. X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=148c8e639da7ee10fc9e002e3c6d60e17d218b21;p=mesa.git i965: Use sendc for all render target writes on Gen6+. The sendc instruction causes the fragment shader thread to wait for any dependent threads (i.e. threads rendering to overlapping pixels) to complete before sending the message. We need to use sendc on the first render target write in order to guarantee that fragment shader outputs are written to the render target in the correct order. Previously, we only used the "sendc" instruction when writing to binding table index 0. This did the right thing for fragment shaders, because our fragment shader back-ends always issue their first render target write to binding table index 0. However, it did the wrong thing for blorp, which performs its render target writes to binding table index 1. A more robust solution is to use sendc for all render target writes. This should not produce any performance penalty, since after the first sendc, all of the dependent threads will have completed. For more information about sendc, see the Ivy Bridge PRM, Vol4 Part3 p218 (sendc - Conditional Send Message), and p54 (TDR Registers). Reviewed-by: Kenneth Graunke Reviewed-by: Eric Anholt --- diff --git a/src/mesa/drivers/dri/i965/brw_eu_emit.c b/src/mesa/drivers/dri/i965/brw_eu_emit.c index 93e84ae54bd..25bf91be532 100644 --- a/src/mesa/drivers/dri/i965/brw_eu_emit.c +++ b/src/mesa/drivers/dri/i965/brw_eu_emit.c @@ -2259,7 +2259,7 @@ void brw_fb_WRITE(struct brw_compile *p, else dest = retype(vec8(brw_null_reg()), BRW_REGISTER_TYPE_UW); - if (intel->gen >= 6 && binding_table_index == 0) { + if (intel->gen >= 6) { insn = next_insn(p, BRW_OPCODE_SENDC); } else { insn = next_insn(p, BRW_OPCODE_SEND);