From: R Veera Kumar <vklr@vkten.in>
Date: Sun, 21 Nov 2021 14:16:02 +0000 (+0530)
Subject: Add expected state to case_cmp in alu_cases unit test
X-Git-Tag: sv_maxu_works-initial~727
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=14bd38a486f8dfc025a5c438c1ead54a657f0e10;p=openpower-isa.git

Add expected state to case_cmp in alu_cases unit test
---

diff --git a/src/openpower/test/alu/alu_cases.py b/src/openpower/test/alu/alu_cases.py
index e743f749..f3695e0b 100644
--- a/src/openpower/test/alu/alu_cases.py
+++ b/src/openpower/test/alu/alu_cases.py
@@ -214,7 +214,13 @@ class ALUTestCase(TestAccumulatorBase):
         initial_regs = [0] * 32
         initial_regs[6] = 0x10
         initial_regs[7] = 0x05
-        self.add_case(Program(lst, bigendian), initial_regs, {})
+        e = ExpectedState(pc=8)
+        e.intregs[6] = 0x10
+        e.intregs[7] = 0x5
+        e.intregs[1] = 0xfffffffffffffff5
+        e.crregs[0] = 0x8
+        e.crregs[2] = 0x4
+        self.add_case(Program(lst, bigendian), initial_regs, expected=e)
 
     def case_cmp2(self):
         lst = ["cmp cr2, 0, 2, 3"]