From: Dave Airlie Date: Fri, 1 Oct 2010 04:00:27 +0000 (+1000) Subject: r600g: add cb flushing for extra buffers + depth buffer on r600/evergreen X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=14c95bb4eec4417887ae882c39fead47624f0fda;p=mesa.git r600g: add cb flushing for extra buffers + depth buffer on r600/evergreen --- diff --git a/src/gallium/drivers/r600/evergreend.h b/src/gallium/drivers/r600/evergreend.h index f9328c61983..3cb9e634f71 100644 --- a/src/gallium/drivers/r600/evergreend.h +++ b/src/gallium/drivers/r600/evergreend.h @@ -1865,9 +1865,18 @@ #define S_0085F0_DB_DEST_BASE_ENA(x) (((x) & 0x1) << 14) #define G_0085F0_DB_DEST_BASE_ENA(x) (((x) >> 14) & 0x1) #define C_0085F0_DB_DEST_BASE_ENA 0xFFFFBFFF -#define S_0085F0_CR_DEST_BASE_ENA(x) (((x) & 0x1) << 15) -#define G_0085F0_CR_DEST_BASE_ENA(x) (((x) >> 15) & 0x1) -#define C_0085F0_CR_DEST_BASE_ENA 0xFFFF7FFF +#define S_0085F0_CB8_DEST_BASE_ENA(x) (((x) & 0x1) << 15) +#define G_0085F0_CB8_DEST_BASE_ENA(x) (((x) >> 15) & 0x1) + +#define S_0085F0_CB9_DEST_BASE_ENA(x) (((x) & 0x1) << 16) +#define G_0085F0_CB9_DEST_BASE_ENA(x) (((x) >> 16) & 0x1) + +#define S_0085F0_CB10_DEST_BASE_ENA(x) (((x) & 0x1) << 17) +#define G_0085F0_CB10_DEST_BASE_ENA(x) (((x) >> 17) & 0x1) + +#define S_0085F0_CB11_DEST_BASE_ENA(x) (((x) & 0x1) << 18) +#define G_0085F0_CB11_DEST_BASE_ENA(x) (((x) >> 18) & 0x1) + #define S_0085F0_TC_ACTION_ENA(x) (((x) & 0x1) << 23) #define G_0085F0_TC_ACTION_ENA(x) (((x) >> 23) & 0x1) #define C_0085F0_TC_ACTION_ENA 0xFF7FFFFF diff --git a/src/gallium/winsys/r600/drm/evergreen_hw_context.c b/src/gallium/winsys/r600/drm/evergreen_hw_context.c index 1b2c2655b50..88db69c4f7d 100644 --- a/src/gallium/winsys/r600/drm/evergreen_hw_context.c +++ b/src/gallium/winsys/r600/drm/evergreen_hw_context.c @@ -727,6 +727,7 @@ void evergreen_context_pipe_state_set_vs_sampler(struct r600_context *ctx, struc void evergreen_context_draw(struct r600_context *ctx, const struct r600_draw *draw) { struct radeon_bo *cb[12]; + struct radeon_bo *db; unsigned ndwords = 9; if (draw->indices) { @@ -738,6 +739,7 @@ void evergreen_context_draw(struct r600_context *ctx, const struct r600_draw *dr } /* find number of color buffer */ + db = r600_context_reg_bo(ctx, R_028048_DB_Z_READ_BASE); cb[0] = r600_context_reg_bo(ctx, R_028C60_CB_COLOR0_BASE); cb[1] = r600_context_reg_bo(ctx, R_028C9C_CB_COLOR1_BASE); cb[2] = r600_context_reg_bo(ctx, R_028CD8_CB_COLOR2_BASE); @@ -755,6 +757,8 @@ void evergreen_context_draw(struct r600_context *ctx, const struct r600_draw *dr ndwords += 7; } } + if (db) + ndwords += 7; /* queries need some special values */ if (ctx->num_query_running) { @@ -808,11 +812,15 @@ void evergreen_context_draw(struct r600_context *ctx, const struct r600_draw *dr ctx->pm4[ctx->pm4_cdwords++] = EVENT_TYPE_CACHE_FLUSH_AND_INV_EVENT; /* flush color buffer */ - for (int i = 0; i < 8; i++) { + for (int i = 0; i < 12; i++) { if (cb[i]) { ctx->pm4[ctx->pm4_cdwords++] = PKT3(PKT3_SURFACE_SYNC, 3); - ctx->pm4[ctx->pm4_cdwords++] = (S_0085F0_CB0_DEST_BASE_ENA(1) << i) | - S_0085F0_CB_ACTION_ENA(1); + if (i > 7) + ctx->pm4[ctx->pm4_cdwords++] = (S_0085F0_CB8_DEST_BASE_ENA(1) << (i - 8)) | + S_0085F0_CB_ACTION_ENA(1); + else + ctx->pm4[ctx->pm4_cdwords++] = (S_0085F0_CB0_DEST_BASE_ENA(1) << i) | + S_0085F0_CB_ACTION_ENA(1); ctx->pm4[ctx->pm4_cdwords++] = (cb[i]->size + 255) >> 8; ctx->pm4[ctx->pm4_cdwords++] = 0x00000000; ctx->pm4[ctx->pm4_cdwords++] = 0x0000000A; @@ -821,6 +829,17 @@ void evergreen_context_draw(struct r600_context *ctx, const struct r600_draw *dr r600_context_bo_reloc(ctx, &ctx->pm4[ctx->pm4_cdwords - 1], cb[i]); } } + if (db) { + ctx->pm4[ctx->pm4_cdwords++] = PKT3(PKT3_SURFACE_SYNC, 3); + ctx->pm4[ctx->pm4_cdwords++] = S_0085F0_DB_DEST_BASE_ENA(1) | + S_0085F0_DB_ACTION_ENA(1); + ctx->pm4[ctx->pm4_cdwords++] = (db->size + 255) >> 8; + ctx->pm4[ctx->pm4_cdwords++] = 0x00000000; + ctx->pm4[ctx->pm4_cdwords++] = 0x0000000A; + ctx->pm4[ctx->pm4_cdwords++] = PKT3(PKT3_NOP, 0); + ctx->pm4[ctx->pm4_cdwords++] = 0; + r600_context_bo_reloc(ctx, &ctx->pm4[ctx->pm4_cdwords - 1], db); + } /* all dirty state have been scheduled in current cs */ ctx->pm4_dirty_cdwords = 0; diff --git a/src/gallium/winsys/r600/drm/r600_hw_context.c b/src/gallium/winsys/r600/drm/r600_hw_context.c index 88a86d2cf28..4d7547c9758 100644 --- a/src/gallium/winsys/r600/drm/r600_hw_context.c +++ b/src/gallium/winsys/r600/drm/r600_hw_context.c @@ -878,6 +878,7 @@ struct radeon_bo *r600_context_reg_bo(struct r600_context *ctx, unsigned offset) void r600_context_draw(struct r600_context *ctx, const struct r600_draw *draw) { struct radeon_bo *cb[8]; + struct radeon_bo *db; unsigned ndwords = 9; if (draw->indices) { @@ -889,6 +890,7 @@ void r600_context_draw(struct r600_context *ctx, const struct r600_draw *draw) } /* find number of color buffer */ + db = r600_context_reg_bo(ctx, R_02800C_DB_DEPTH_BASE); cb[0] = r600_context_reg_bo(ctx, R_028040_CB_COLOR0_BASE); cb[1] = r600_context_reg_bo(ctx, R_028044_CB_COLOR1_BASE); cb[2] = r600_context_reg_bo(ctx, R_028048_CB_COLOR2_BASE); @@ -902,6 +904,8 @@ void r600_context_draw(struct r600_context *ctx, const struct r600_draw *draw) ndwords += 7; } } + if (db) + ndwords += 7; /* queries need some special values */ if (ctx->num_query_running) { @@ -970,6 +974,17 @@ void r600_context_draw(struct r600_context *ctx, const struct r600_draw *draw) r600_context_bo_reloc(ctx, &ctx->pm4[ctx->pm4_cdwords - 1], cb[i]); } } + if (db) { + ctx->pm4[ctx->pm4_cdwords++] = PKT3(PKT3_SURFACE_SYNC, 3); + ctx->pm4[ctx->pm4_cdwords++] = S_0085F0_DB_DEST_BASE_ENA(1) | + S_0085F0_DB_ACTION_ENA(1); + ctx->pm4[ctx->pm4_cdwords++] = (db->size + 255) >> 8; + ctx->pm4[ctx->pm4_cdwords++] = 0x00000000; + ctx->pm4[ctx->pm4_cdwords++] = 0x0000000A; + ctx->pm4[ctx->pm4_cdwords++] = PKT3(PKT3_NOP, 0); + ctx->pm4[ctx->pm4_cdwords++] = 0; + r600_context_bo_reloc(ctx, &ctx->pm4[ctx->pm4_cdwords - 1], db); + } /* all dirty state have been scheduled in current cs */ ctx->pm4_dirty_cdwords = 0;