From: whitequark <whitequark@whitequark.org>
Date: Fri, 5 Mar 2021 12:08:48 +0000 (+0000)
Subject: cxxrtl: follow aliases to outlines when emitting $memrd.ADDR.
X-Git-Tag: working-ls180~14^2
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=14ce8bdaa6a1120c48a934697488c463ffb15b48;p=yosys.git

cxxrtl: follow aliases to outlines when emitting $memrd.ADDR.
---

diff --git a/backends/cxxrtl/cxxrtl_backend.cc b/backends/cxxrtl/cxxrtl_backend.cc
index 39046bd78..f2ff8a468 100644
--- a/backends/cxxrtl/cxxrtl_backend.cc
+++ b/backends/cxxrtl/cxxrtl_backend.cc
@@ -1231,7 +1231,9 @@ struct CxxrtlWorker {
 			RTLIL::Memory *memory = cell->module->memories[cell->getParam(ID::MEMID).decode_string()];
 			std::string valid_index_temp = fresh_temporary();
 			f << indent << "auto " << valid_index_temp << " = memory_index(";
-			dump_sigspec_rhs(cell->getPort(ID::ADDR));
+			// Almost all non-elidable cells cannot appear in debug_eval(), but $memrd is an exception; asynchronous
+			// memory read ports can.
+			dump_sigspec_rhs(cell->getPort(ID::ADDR), for_debug);
 			f << ", " << memory->start_offset << ", " << memory->size << ");\n";
 			if (cell->type == ID($memrd)) {
 				bool has_enable = cell->getParam(ID::CLK_ENABLE).as_bool() && !cell->getPort(ID::EN).is_fully_ones();