From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Sun, 18 Sep 2022 13:34:15 +0000 (+0100)
Subject: adapt test_12_mr to /mrr and /mr modes, svm is gone, /mr is missing
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=14e8214ccf3e4443b4b813b607ffbc173f123477;p=openpower-isa.git

adapt test_12_mr to /mrr and /mr modes, svm is gone, /mr is missing
---

diff --git a/src/openpower/sv/trans/test_pysvp64dis.py b/src/openpower/sv/trans/test_pysvp64dis.py
index 2c290b05..40ef39a5 100644
--- a/src/openpower/sv/trans/test_pysvp64dis.py
+++ b/src/openpower/sv/trans/test_pysvp64dis.py
@@ -204,10 +204,12 @@ class SVSTATETestCase(unittest.TestCase):
                         ]
         self._do_tst(expected)
 
-    def test_12_smr_svmr(self):
+    def test_12_mr_r(self):
         expected = [
                     "sv.add./mrr/vec2 *3,*7,*11",
-                    "sv.add./svm/vec4 *3,*7,*11",
+                    "sv.add./mr/vec2 *3,*7,*11",
+                    "sv.add./mrr *3,*7,*11",
+                    "sv.add./mr *3,*7,*11",
                         ]
         self._do_tst(expected)