From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Tue, 22 Sep 2020 14:42:57 +0000 (+0100)
Subject: create a JTAG platform and connect it up.  jtagremote is actually running
X-Git-Tag: 24jan2021_ls180~349
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=14f09a6cba595d2f9fa3b21a9eee2ff22b56d2c4;p=soc.git

create a JTAG platform and connect it up.  jtagremote is actually running
---

diff --git a/src/soc/litex/florent/sim.py b/src/soc/litex/florent/sim.py
index 87521ebd..c797a43d 100755
--- a/src/soc/litex/florent/sim.py
+++ b/src/soc/litex/florent/sim.py
@@ -164,6 +164,23 @@ class LibreSoCSim(SoCSDRAM):
             self.add_constant("MEMTEST_DATA_DEBUG", 1)
 
 
+        # add JTAG platform pins
+        platform.add_extension([
+            ("jtag", 0,
+                Subsignal("tck",  Pins(1)),
+                Subsignal("tms", Pins(1)),
+                Subsignal("tdi", Pins(1)),
+                Subsignal("tdo", Pins(1)),
+            )
+        ])
+
+        jtagpads = platform.request("jtag")
+        self.comb += self.cpu.jtag_tck.eq(jtagpads.tck)
+        self.comb += self.cpu.jtag_tms.eq(jtagpads.tms)
+        self.comb += self.cpu.jtag_tdi.eq(jtagpads.tdi)
+        self.comb += jtagpads.tdo.eq(self.cpu.jtag_tdo)
+
+
         # Debug ---------------------------------------------------------------
         if not debug:
             return