From: Jacob Lifshay <programmerjake@gmail.com>
Date: Tue, 7 Mar 2023 04:43:24 +0000 (-0800)
Subject: convert notes column to bullet list entry instead
X-Git-Tag: opf_rfc_ls001_v3~191
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=14fc89d93065c3eebf2fe29cdae1695f6c636d7f;p=libreriscv.git

convert notes column to bullet list entry instead
---

diff --git a/openpower/sv/int_fp_mv_reduced_insn_count.mdwn b/openpower/sv/int_fp_mv_reduced_insn_count.mdwn
index efc36804e..2329f034a 100644
--- a/openpower/sv/int_fp_mv_reduced_insn_count.mdwn
+++ b/openpower/sv/int_fp_mv_reduced_insn_count.mdwn
@@ -24,17 +24,18 @@ Attempt at [reducing the number of different instructions](#reduced-instruction-
 
 ## reduced instruction list <a name="reduced-instruction-list"></a>
 
-| old                                  | new                                        | notes                               |
-|--------------------------------------|--------------------------------------------|-------------------------------------|
-| `fmvis FRS, D`                       | `fmvis FRS, D`                             | submitted to ISA WG so don't modify |
-| `fishmv FRS, D`                      | `fishmv FRS, D`                            | submitted to ISA WG so don't modify |
-| `fmvtg[s][.] RT, FRA`                | `fmvtg RT, FRA, S_AND_RC`                  | goes against PowerISA naming scheme |
-| `fmvfg[s][.] FRT, RA`                | `fmvfg FRT, RA, S_AND_RC`                  | goes against PowerISA naming scheme |
-| `fcvtfg[u][w/d][s][.] FRT, RA`       | `fcvtfg FRT, RA, S_AND_RC, INT_MODE`       | goes against PowerISA naming scheme |
-| `fcvt[s]tg[u][w/d][.] RT, FRA, Mode` | `fcvttg RT, FRA, Mode, S_AND_RC, INT_MODE` | goes against PowerISA naming scheme |
+| old                                  | new                                        |
+|--------------------------------------|--------------------------------------------|
+| `fmvis FRS, D`                       | `fmvis FRS, D`                             |
+| `fishmv FRS, D`                      | `fishmv FRS, D`                            |
+| `fmvtg[s][.] RT, FRA`                | `fmvtg RT, FRA, S_AND_RC`                  |
+| `fmvfg[s][.] FRT, RA`                | `fmvfg FRT, RA, S_AND_RC`                  |
+| `fcvtfg[u][w/d][s][.] FRT, RA`       | `fcvtfg FRT, RA, S_AND_RC, INT_MODE`       |
+| `fcvt[s]tg[u][w/d][.] RT, FRA, Mode` | `fcvttg RT, FRA, Mode, S_AND_RC, INT_MODE` |
 
 Notes:
 
+* `fmvis` and `fishmv` have already been submitted to the ISA WG, so don't modify them!
 * PowerISA uses `s` and `.` suffixes instead of an immediate for Single and Rc=1 modes respectively.
 * PowerISA uses `w`, `uw`, `d`, and `ud` suffixes instead of an immediate for selecting between unsigned/signed 32-bit/64-bit.
 * About the only operations we can realistically remove are Rc=1 versions, however Jacob thinks that isn't necessary.