From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Tue, 6 Nov 2018 11:33:26 +0000 (+0000)
Subject: pass in extra arg (bitwidth) into rv_sr
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=150522b1a8915cd4706cf8b1d5da31b2e91738cc;p=riscv-isa-sim.git

pass in extra arg (bitwidth) into rv_sr
---

diff --git a/riscv/insns/sra.h b/riscv/insns/sra.h
index 5f0586f..52b30a8 100644
--- a/riscv/insns/sra.h
+++ b/riscv/insns/sra.h
@@ -1,2 +1 @@
-WRITE_RD(sext_xlen(rv_sr(sext_xlen(RS1),
-                         rv_and(RS2, sv_reg_t(xlen-1)))));
+WRITE_RD(sext_xlen(rv_sr(sext_xlen(RS1), RS2, xlen)));
diff --git a/riscv/insns/srai.h b/riscv/insns/srai.h
index 2de77e3..86b2025 100644
--- a/riscv/insns/srai.h
+++ b/riscv/insns/srai.h
@@ -1,2 +1,2 @@
 require(rv_lt(SHAMT, sv_reg_t(xlen)));
-WRITE_RD(sext_xlen(rv_sr(sext_xlen(RS1), SHAMT)));
+WRITE_RD(sext_xlen(rv_sr(sext_xlen(RS1), SHAMT, 64)));
diff --git a/riscv/insns/sraiw.h b/riscv/insns/sraiw.h
index 6c4d332..31b3b76 100644
--- a/riscv/insns/sraiw.h
+++ b/riscv/insns/sraiw.h
@@ -1,2 +1,2 @@
 require_rv64;
-WRITE_RD(sext32(rv_sr(sv_reg_int32(RS1), SHAMT)));
+WRITE_RD(sext32(rv_sr(sv_reg_int32(RS1), SHAMT, 64)));
diff --git a/riscv/insns/sraw.h b/riscv/insns/sraw.h
index 99d3e21..83607f9 100644
--- a/riscv/insns/sraw.h
+++ b/riscv/insns/sraw.h
@@ -1,2 +1,2 @@
 require_rv64;
-WRITE_RD(sext32(rv_sr(sv_reg_int32(RS1), RS2, 0x1FU)));
+WRITE_RD(sext32(rv_sr(sv_reg_int32(RS1), RS2, 32U)));
diff --git a/riscv/insns/srl.h b/riscv/insns/srl.h
index c51d2ad..1d854c1 100644
--- a/riscv/insns/srl.h
+++ b/riscv/insns/srl.h
@@ -1,2 +1 @@
-WRITE_RD(sext_xlen(rv_sr(zext_xlen(RS1),
-                         rv_and(RS2, sv_reg_t(xlen-1)))));
+WRITE_RD(sext_xlen(rv_sr(zext_xlen(RS1), RS2, xlen)));
diff --git a/riscv/insns/srli.h b/riscv/insns/srli.h
index bca4c83..e87caba 100644
--- a/riscv/insns/srli.h
+++ b/riscv/insns/srli.h
@@ -1,2 +1,2 @@
 require(rv_lt(SHAMT, sv_reg_t(xlen)));
-WRITE_RD(sext_xlen(rv_sr(zext_xlen(RS1), SHAMT)));
+WRITE_RD(sext_xlen(rv_sr(zext_xlen(RS1), SHAMT, 64)));
diff --git a/riscv/insns/srliw.h b/riscv/insns/srliw.h
index 357c724..4dfc0ed 100644
--- a/riscv/insns/srliw.h
+++ b/riscv/insns/srliw.h
@@ -1,2 +1,2 @@
 require_rv64;
-WRITE_RD(sext32(rv_sr(sv_reg_uint32(RS1), SHAMT)));
+WRITE_RD(sext32(rv_sr(sv_reg_uint32(RS1), SHAMT, 64)));
diff --git a/riscv/insns/srlw.h b/riscv/insns/srlw.h
index 34b574e..2cf8cef 100644
--- a/riscv/insns/srlw.h
+++ b/riscv/insns/srlw.h
@@ -1,3 +1,2 @@
 require_rv64;
-WRITE_RD(sext32(rv_sr(sv_reg_uint32(RS1),
-                      rv_and(RS2, sv_reg_t(0x1FU)))));
+WRITE_RD(sext32(rv_sr(sv_reg_uint32(RS1), RS2, 32U)));