From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Mon, 15 May 2023 20:47:18 +0000 (+0100)
Subject: add "WRONG" sv.cmp in test_pysvp64dis.py
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=150a43594b0702320d553578fec6d8ea5782c7e6;p=openpower-isa.git

add "WRONG" sv.cmp in test_pysvp64dis.py
---

diff --git a/src/openpower/sv/trans/test_pysvp64dis.py b/src/openpower/sv/trans/test_pysvp64dis.py
index 2fa01642..56828cb4 100644
--- a/src/openpower/sv/trans/test_pysvp64dis.py
+++ b/src/openpower/sv/trans/test_pysvp64dis.py
@@ -321,6 +321,7 @@ class SVSTATETestCase(unittest.TestCase):
                     "sv.cmp/ff=eq/m=r3/zz *4,1,*0,1",
                     "sv.cmp/ff=lt/m=r3/zz *4,1,*0,1",
                     "sv.cmp/ff=gt/m=r3/zz *4,1,*0,1",
+                    "sv.cmp/zz/ff=gt/m=r3 *4,1,*0,1", # WRONG
                         ]
         self._do_tst(expected)