From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Sat, 10 Nov 2018 20:08:29 +0000 (+0000)
Subject: macro-ify 64-bit mulh fns
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=1513f522cf93ef6d11ecb98c8cbcdaa1857dd749;p=riscv-isa-sim.git

macro-ify 64-bit mulh fns
---

diff --git a/riscv/sv_insn_redirect.cc b/riscv/sv_insn_redirect.cc
index 3ce22f3..b82d3f0 100644
--- a/riscv/sv_insn_redirect.cc
+++ b/riscv/sv_insn_redirect.cc
@@ -566,30 +566,26 @@ OP_MULH_FN(_mulh  , sv_sreg_t, sv_sreg_t, sv_sreg_t, int64_t, int64_t, int64_t )
    only when both source registers are <= 32 bit can we use
    the 32-bit rv_mulh.
  */
-sv_reg_t (sv_proc_t::mulhu)(sv_reg_t const& lhs, sv_reg_t const& rhs)
-{
+#define OP_M64_FN( fname, SLHSTYPE, SRHSTYPE, SRESTYPE, \
+                           LHSTYPE, RHSTYPE, RESTYPE ) \
+SRESTYPE sv_proc_t::fname (SLHSTYPE const & lhs, SRHSTYPE const & rhs) \
+{                                                                        \
     uint8_t bitwidth = _insn->src_bitwidth;                                  \
-    uint64_t vlhs = 0;                                                       \
-    uint64_t vrhs = 0;                                                       \
+    LHSTYPE vlhs = 0;                                                       \
+    RHSTYPE vrhs = 0;                                                       \
     if (rv_int_op_prepare(lhs, rhs, vlhs, vrhs, bitwidth) ||                 \
         lhs.get_elwidth() == 0 || rhs.get_elwidth() == 0 ) {                 \
-        uint64_t result = ::mulhu(vlhs, vrhs);
-        fprintf(stderr, "%s result %lx %lx %lx\n",               \
-                "mulhu", (uint64_t)vlhs, (uint64_t)vrhs, (uint64_t)result);  \
+        RESTYPE result = ::fname(vlhs, vrhs);                              \
+        fprintf(stderr, "%s result %lx %lx %lx\n",                            \
+                xstr(fname), (LHSTYPE)lhs, (RHSTYPE)rhs, (RESTYPE)result);  \
         return rv_int_op_finish(lhs, rhs, result, bitwidth);                 \
     }                                                                        \
-    return rv_mulh(lhs, rhs);
-}
-
-sv_sreg_t (sv_proc_t::mulhsu)(sv_sreg_t const& a, sv_reg_t const& b)
-{
-    return sv_sreg_t(::mulhsu(a, b));
+    return rv_##fname(lhs, rhs);                                             \
 }
 
-sv_sreg_t (sv_proc_t::mulh)(sv_sreg_t const& a, sv_sreg_t const& b)
-{
-    return sv_sreg_t(::mulh(a, b));
-}
+OP_M64_FN( mulhu , sv_reg_t, sv_reg_t, sv_reg_t, uint64_t, uint64_t, uint64_t )
+OP_M64_FN( mulhsu, sv_sreg_t, sv_reg_t, sv_sreg_t, int64_t, uint64_t, int64_t )
+OP_M64_FN( mulh  , sv_sreg_t, sv_sreg_t, sv_sreg_t, int64_t, int64_t, int64_t )
 
 sv_reg_t sv_proc_t::rv_sl(sv_reg_t const & lhs, sv_reg_t const & rhs)
 {