From: Francisco Jerez <currojerez@riseup.net>
Date: Tue, 6 Aug 2019 01:21:05 +0000 (-0700)
Subject: intel/ir: Represent logical edge of BREAK instruction.
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=152754665abb937a49e451331c88266ef5c3cdf1;p=mesa.git

intel/ir: Represent logical edge of BREAK instruction.

Currently only the physical back-edge is represented, which
incidentally also leads to the exit block of the loop, but we need the
direct logical edge in addition for our logical CFG representation to
be complete.

Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira@intel.com>
---

diff --git a/src/intel/compiler/brw_cfg.cpp b/src/intel/compiler/brw_cfg.cpp
index d5e8913e058..70a7530e265 100644
--- a/src/intel/compiler/brw_cfg.cpp
+++ b/src/intel/compiler/brw_cfg.cpp
@@ -352,6 +352,7 @@ cfg_t::cfg_t(exec_list *instructions)
           */
          assert(cur_do != NULL);
          cur->add_successor(mem_ctx, cur_do, bblock_link_physical);
+         cur->add_successor(mem_ctx, cur_while, bblock_link_logical);
 
 	 next = new_block();
 	 if (inst->predicate)