From: lkcl Date: Thu, 7 Jan 2021 16:49:27 +0000 (+0000) Subject: (no commit message) X-Git-Tag: convert-csv-opcode-to-binary~580 X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=1527f49f217b66360f9714dad487fe044d6380c8;p=libreriscv.git --- diff --git a/openpower/sv/setvl.mdwn b/openpower/sv/setvl.mdwn index 6ef7105ef..d8ae0f4c3 100644 --- a/openpower/sv/setvl.mdwn +++ b/openpower/sv/setvl.mdwn @@ -33,7 +33,7 @@ instructions: setvli r0, MVL=64, VL=64 ld r0.v, 0(r30) # load 64 registers from memory -This is *guaranteed* 100% without fail to perform 64 unit-strided LDs starting from the address pointed to by r30 and put the contents into r0 through r63. Thus it becomes a "LOAD-MULTI". Twin Predication could even be used to only load relevant registers from the stack. This *only works if VL is set to the requested value* (caveat being, limited to not exceed MVL) +Page Faults etc. aside this is *guaranteed* 100% without fail to perform 64 unit-strided LDs starting from the address pointed to by r30 and put the contents into r0 through r63. Thus it becomes a "LOAD-MULTI". Twin Predication could even be used to only load relevant registers from the stack. This *only works if VL is set to the requested value* (caveat being, limited to not exceed MVL) # Format