From: Uros Bizjak <ubizjak@gmail.com>
Date: Tue, 3 Jul 2018 17:33:28 +0000 (+0200)
Subject: re PR tree-optimization/85694 (Generation of vectorized AVG (Average) instruction)
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=15333be70addf4eb750d82d5e298cd3ad33b711a;p=gcc.git

re PR tree-optimization/85694 (Generation of vectorized AVG (Average) instruction)

	PR target/85694
	* config/i386/sse.md (uavg<mode>3_ceil): New expander.
	(<sse2_avx2>_uavg<mode>3<mask_name>): Simplify expander.

testsuite/ChangeLog:

	PR target/85694
	* gcc.target/i386/pr85694.c: New test.

From-SVN: r262354
---

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index 4c550b6f3e4..7f5fa7b97df 100644
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,9 @@
+2018-07-03  Uros Bizjak  <ubizjak@gmail.com>
+
+	PR target/85694
+	* config/i386/sse.md (uavg<mode>3_ceil): New expander.
+	(<sse2_avx2>_uavg<mode>3<mask_name>): Simplify expander.
+
 2018-07-03  Richard Sandiford  <richard.sandiford@arm.com>
 
 	PR tree-optimization/85694
diff --git a/gcc/config/i386/sse.md b/gcc/config/i386/sse.md
index 0420da8035c..d2722fdfcd0 100644
--- a/gcc/config/i386/sse.md
+++ b/gcc/config/i386/sse.md
@@ -10764,6 +10764,24 @@
   DONE;
 })
 
+(define_expand "uavg<mode>3_ceil"
+  [(set (match_operand:VI12_AVX2 0 "register_operand")
+	(truncate:VI12_AVX2
+	  (lshiftrt:<ssedoublemode>
+	    (plus:<ssedoublemode>
+	      (plus:<ssedoublemode>
+		(zero_extend:<ssedoublemode>
+		  (match_operand:VI12_AVX2 1 "vector_operand"))
+		(zero_extend:<ssedoublemode>
+		  (match_operand:VI12_AVX2 2 "vector_operand")))
+	      (match_dup 3))
+	    (const_int 1))))]
+  "TARGET_SSE2"
+{
+  operands[3] = CONST1_RTX(<MODE>mode);
+  ix86_fixup_binary_operands_no_copy (PLUS, <MODE>mode, operands);
+})
+
 (define_expand "usadv16qi"
   [(match_operand:V4SI 0 "register_operand")
    (match_operand:V16QI 1 "register_operand")
@@ -14234,17 +14252,8 @@
 	    (const_int 1))))]
   "TARGET_SSE2 && <mask_mode512bit_condition> && <mask_avx512bw_condition>"
 {
-  rtx tmp;
-  if (<mask_applied>)
-    tmp = operands[3];
-  operands[3] = CONST1_RTX(<MODE>mode);
+  operands[<mask_expand_op3>] = CONST1_RTX(<MODE>mode);
   ix86_fixup_binary_operands_no_copy (PLUS, <MODE>mode, operands);
-
-  if (<mask_applied>)
-    {
-      operands[5] = operands[3];
-      operands[3] = tmp;
-    }
 })
 
 (define_insn "*<sse2_avx2>_uavg<mode>3<mask_name>"
diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog
index 2afad58666b..d18061088b8 100644
--- a/gcc/testsuite/ChangeLog
+++ b/gcc/testsuite/ChangeLog
@@ -3,6 +3,11 @@
 	PR c++/86201
 	* g++.dg/diagnostic/pr86201.C: New test.
 
+2018-07-03  Uros Bizjak  <ubizjak@gmail.com>
+
+	PR target/85694
+	* gcc.target/i386/pr85694.c: New test.
+
 2018-07-03  Richard Sandiford  <richard.sandiford@arm.com>
 
 	PR tree-optimization/85694
diff --git a/gcc/testsuite/gcc.target/i386/pr85694.c b/gcc/testsuite/gcc.target/i386/pr85694.c
new file mode 100644
index 00000000000..b730d23c70b
--- /dev/null
+++ b/gcc/testsuite/gcc.target/i386/pr85694.c
@@ -0,0 +1,18 @@
+/* { dg-do compile }
+/* { dg-options "-msse2 -O2 -ftree-vectorize" } */
+/* { dg-final { scan-assembler "pavgb" } } */
+/* { dg-final { scan-assembler "pavgw" } } */
+
+#define N 1024
+
+#define TEST(TYPE)						\
+  unsigned TYPE a_##TYPE[N], b_##TYPE[N], c_##TYPE[N];		\
+  void f_##TYPE (void)						\
+  {								\
+    int i;							\
+    for (i = 0; i < N; i++)					\
+      a_##TYPE[i] = (b_##TYPE[i] + c_##TYPE[i] + 1) >> 1;	\
+  }
+
+TEST(char);
+TEST(short);