From: SergeyDegtyar Date: Tue, 20 Aug 2019 04:50:05 +0000 (+0300) Subject: Add new tests for ice40 architecture X-Git-Tag: working-ls180~1084^2~25 X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=153ec0541c17ee8fad093c002a2724bc33dfe4b9;p=yosys.git Add new tests for ice40 architecture --- diff --git a/Makefile b/Makefile index 382f79546..9cfa6a0de 100644 --- a/Makefile +++ b/Makefile @@ -699,6 +699,7 @@ test: $(TARGETS) $(EXTRA_TARGETS) +cd tests/opt && bash run-test.sh +cd tests/aiger && bash run-test.sh $(ABCOPT) +cd tests/arch && bash run-test.sh + +cd tests/ice40 && bash run-test.sh $(SEEDOPT) @echo "" @echo " Passed \"make test\"." @echo "" diff --git a/tests/ice40/.gitignore b/tests/ice40/.gitignore new file mode 100644 index 000000000..397b4a762 --- /dev/null +++ b/tests/ice40/.gitignore @@ -0,0 +1 @@ +*.log diff --git a/tests/ice40/add_sub.ys b/tests/ice40/add_sub.ys new file mode 100644 index 000000000..58ad52a58 --- /dev/null +++ b/tests/ice40/add_sub.ys @@ -0,0 +1,7 @@ +equiv_opt -map ../../techlibs/ice40/cells_sim.v synth_ice40 +synth_ice40 +select -assert-count 12 t:SB_LUT4 +select -assert-count 7 t:SB_CARRY +select -assert-count 2 t:$logic_and +select -assert-count 2 t:$logic_or +write_verilog ./temp/add_sub_synth.v diff --git a/tests/ice40/add_sub_tb.v b/tests/ice40/add_sub_tb.v new file mode 100644 index 000000000..45e4f3154 --- /dev/null +++ b/tests/ice40/add_sub_tb.v @@ -0,0 +1,47 @@ +module testbench; + reg [7:0] in; + + wire [3:0] outA,outB; + wire [3:0] poutA,poutB; + + initial begin + // $dumpfile("testbench.vcd"); + // $dumpvars(0, testbench); + + #5 in = 0; + repeat (10000) begin + #5 in = in + 1; + end + + $display("OKAY"); + end + + top uut ( + .x(in[3:0]), + .y(in[7:4]), + .A(outA), + .B(outB) + ); + + + assign poutA = in[3:0] + in[7:4]; + assign poutB = in[3:0] - in[7:4]; + + check_comb add_test(outA, poutA); + check_comb sub_test(outB, poutB); + assert_comb sub0_test(outB[2], poutB[2]); + +endmodule + +module check_comb(input [3:0] test, input [3:0] pat); + always @* + begin + #1; + if (test != pat) + begin + $display("ERROR: ASSERTION FAILED in %m:",$time," ",test," ",pat); + $stop; + end + end +endmodule + diff --git a/tests/ice40/add_sub_top.v b/tests/ice40/add_sub_top.v new file mode 100644 index 000000000..177c32e30 --- /dev/null +++ b/tests/ice40/add_sub_top.v @@ -0,0 +1,13 @@ +module top +( + input [3:0] x, + input [3:0] y, + + output [3:0] A, + output [3:0] B + ); + +assign A = x + y; +assign B = x - y; + +endmodule diff --git a/tests/ice40/common.v b/tests/ice40/common.v new file mode 100644 index 000000000..5446f0817 --- /dev/null +++ b/tests/ice40/common.v @@ -0,0 +1,47 @@ +module assert_dff(input clk, input test, input pat); + always @(posedge clk) + begin + #1; + if (test != pat) + begin + $display("ERROR: ASSERTION FAILED in %m:",$time); + $stop; + end + end +endmodule + +module assert_tri(input en, input A, input B); + always @(posedge en) + begin + #1; + if (A !== B) + begin + $display("ERROR: ASSERTION FAILED in %m:",$time," ",A," ",B); + $stop; + end + end +endmodule + +module assert_Z(input clk, input A); + always @(posedge clk) + begin + #1; + if (A === 1'bZ) + begin + $display("ERROR: ASSERTION FAILED in %m:",$time," ",A); + $stop; + end + end +endmodule + +module assert_comb(input A, input B); + always @(*) + begin + #1; + if (A !== B) + begin + $display("ERROR: ASSERTION FAILED in %m:",$time," ",A," ",B); + $stop; + end + end +endmodule diff --git a/tests/ice40/dffs.ys b/tests/ice40/dffs.ys new file mode 100644 index 000000000..68410b4d8 --- /dev/null +++ b/tests/ice40/dffs.ys @@ -0,0 +1,5 @@ +equiv_opt -map ../../techlibs/ice40/cells_sim.v synth_ice40 +synth_ice40 +select -assert-count 2 t:SB_DFFR +select -assert-count 1 t:SB_DFFE +write_verilog ./temp/dffs_synth.v diff --git a/tests/ice40/dffs_tb.v b/tests/ice40/dffs_tb.v new file mode 100644 index 000000000..ed8f2eb2a --- /dev/null +++ b/tests/ice40/dffs_tb.v @@ -0,0 +1,77 @@ +module testbench; + reg clk; + + initial begin + // $dumpfile("testbench.vcd"); + // $dumpvars(0, testbench); + + #5 clk = 0; + repeat (10000) begin + #5 clk = 1; + #5 clk = 0; + end + + $display("OKAY"); + end + + + reg [2:0] dinA = 0; + wire doutB,doutB1,doutB2,doutB3,doutB4; + reg dff,ndff,adff,adffn,dffe = 0; + + top uut ( + .clk (clk ), + .a (dinA[0] ), + .pre (dinA[1] ), + .clr (dinA[2] ), + .b (doutB ), + .b1 (doutB1 ), + .b2 (doutB2 ), + .b3 (doutB3 ), + .b4 (doutB4 ) + ); + + always @(posedge clk) begin + #3; + dinA <= dinA + 1; + end + + always @( posedge clk, posedge dinA[1], posedge dinA[2] ) + if ( dinA[2] ) + dff <= 1'b0; + else if ( dinA[1] ) + dff <= 1'b1; + else + dff <= dinA[0]; + + always @( negedge clk, negedge dinA[1], negedge dinA[2] ) + if ( !dinA[2] ) + ndff <= 1'b0; + else if ( !dinA[1] ) + ndff <= 1'b1; + else + ndff <= dinA[0]; + + always @( posedge clk, posedge dinA[2] ) + if ( dinA[2] ) + adff <= 1'b0; + else + adff <= dinA[0]; + + always @( posedge clk, negedge dinA[2] ) + if ( !dinA[2] ) + adffn <= 1'b0; + else + adffn <= dinA[0]; + + always @( posedge clk ) + if ( dinA[2] ) + dffe <= dinA[0]; + + assert_dff dff_test(.clk(clk), .test(doutB), .pat(dff)); + assert_dff ndff_test(.clk(clk), .test(doutB1), .pat(ndff)); + assert_dff adff_test(.clk(clk), .test(doutB2), .pat(adff)); + assert_dff adffn_test(.clk(clk), .test(doutB3), .pat(adffn)); + assert_dff dffe_test(.clk(clk), .test(doutB4), .pat(dffe)); + +endmodule diff --git a/tests/ice40/dffs_top.v b/tests/ice40/dffs_top.v new file mode 100644 index 000000000..af7022c79 --- /dev/null +++ b/tests/ice40/dffs_top.v @@ -0,0 +1,108 @@ +module adff + ( input d, clk, clr, output reg q ); + initial begin + q = 0; + end + always @( posedge clk, posedge clr ) + if ( clr ) + q <= 1'b0; + else + q <= d; +endmodule + +module adffn + ( input d, clk, clr, output reg q ); + initial begin + q = 0; + end + always @( posedge clk, negedge clr ) + if ( !clr ) + q <= 1'b0; + else + q <= d; +endmodule + +module dffe + ( input d, clk, en, output reg q ); + initial begin + q = 0; + end + always @( posedge clk ) + if ( en ) + q <= d; +endmodule + +module dffsr + ( input d, clk, pre, clr, output reg q ); + initial begin + q = 0; + end + always @( posedge clk, posedge pre, posedge clr ) + if ( clr ) + q <= 1'b0; + else if ( pre ) + q <= 1'b1; + else + q <= d; +endmodule + +module ndffnsnr + ( input d, clk, pre, clr, output reg q ); + initial begin + q = 0; + end + always @( negedge clk, negedge pre, negedge clr ) + if ( !clr ) + q <= 1'b0; + else if ( !pre ) + q <= 1'b1; + else + q <= d; +endmodule + +module top ( +input clk, +input clr, +input pre, +input a, +output b,b1,b2,b3,b4 +); + +dffsr u_dffsr ( + .clk (clk ), + .clr (clr), + .pre (pre), + .d (a ), + .q (b ) + ); + +ndffnsnr u_ndffnsnr ( + .clk (clk ), + .clr (clr), + .pre (pre), + .d (a ), + .q (b1 ) + ); + +adff u_adff ( + .clk (clk ), + .clr (clr), + .d (a ), + .q (b2 ) + ); + +adffn u_adffn ( + .clk (clk ), + .clr (clr), + .d (a ), + .q (b3 ) + ); + +dffe u_dffe ( + .clk (clk ), + .en (clr), + .d (a ), + .q (b4 ) + ); + +endmodule diff --git a/tests/ice40/div_mod.ys b/tests/ice40/div_mod.ys new file mode 100644 index 000000000..28f31136b --- /dev/null +++ b/tests/ice40/div_mod.ys @@ -0,0 +1,5 @@ +synth_ice40 +equiv_opt -map ../../techlibs/ice40/cells_sim.v synth_ice40 +select -assert-count 89 t:SB_LUT4 +select -assert-count 66 t:SB_CARRY +write_verilog ./temp/div_mod_synth.v diff --git a/tests/ice40/div_mod_tb.v b/tests/ice40/div_mod_tb.v new file mode 100644 index 000000000..4296535c9 --- /dev/null +++ b/tests/ice40/div_mod_tb.v @@ -0,0 +1,48 @@ +module testbench; + reg [7:0] in; + + wire [3:0] outA,outB; + wire [3:0] poutA,poutB; + + initial begin + // $dumpfile("testbench.vcd"); + // $dumpvars(0, testbench); + + #5 in = 0; + repeat (10000) begin + #5 in = in + 1; + end + + $display("OKAY"); + end + + top uut ( + .x(in[3:0]), + .y(in[7:4]), + .A(outA), + .B(outB) + ); + + + assign poutA = in[3:0] % in[7:4]; + assign poutB = in[3:0] / in[7:4]; + + check_comb mod_test(in[7:4], outA, poutA); + check_comb div_test(in[7:4], outB, poutB); + //assert_comb div2_test(outB[2], poutB[2]); + +endmodule + +module check_comb(input [3:0] divisor, input [3:0] test, input [3:0] pat); + always @* + begin + #1; + if (divisor != 4'b0000) + if (test !== pat) + begin + $display("ERROR: ASSERTION FAILED in %m:",$time," ",test," ",pat); + $stop; + end + end +endmodule + diff --git a/tests/ice40/div_mod_top.v b/tests/ice40/div_mod_top.v new file mode 100644 index 000000000..64a36707d --- /dev/null +++ b/tests/ice40/div_mod_top.v @@ -0,0 +1,13 @@ +module top +( + input [3:0] x, + input [3:0] y, + + output [3:0] A, + output [3:0] B + ); + +assign A = x % y; +assign B = x / y; + +endmodule diff --git a/tests/ice40/latches.ys b/tests/ice40/latches.ys new file mode 100644 index 000000000..250ea0f84 --- /dev/null +++ b/tests/ice40/latches.ys @@ -0,0 +1,5 @@ +synth_ice40 +equiv_opt -map ../../techlibs/ice40/cells_sim.v synth_ice40 +proc +select -assert-count 5 t:SB_LUT4 +write_verilog ./temp/latches_synth.v diff --git a/tests/ice40/latches_tb.v b/tests/ice40/latches_tb.v new file mode 100644 index 000000000..47ae8670c --- /dev/null +++ b/tests/ice40/latches_tb.v @@ -0,0 +1,59 @@ +module testbench; + reg clk; + + initial begin + // $dumpfile("testbench.vcd"); + // $dumpvars(0, testbench); + + #5 clk = 0; + repeat (10000) begin + #5 clk = 1; + #5 clk = 0; + end + + $display("OKAY"); + end + + + reg [2:0] dinA = 0; + wire doutB,doutB1,doutB2; + reg lat,latn,latsr = 0; + + top uut ( + .clk (clk ), + .a (dinA[0] ), + .pre (dinA[1] ), + .clr (dinA[2] ), + .b (doutB ), + .b1 (doutB1 ), + .b2 (doutB2 ) + ); + + always @(posedge clk) begin + #3; + dinA <= dinA + 1; + end + + always @* + if ( clk ) + lat <= dinA[0]; + + + always @* + if ( !clk ) + latn <= dinA[0]; + + + always @* + if ( dinA[2] ) + latsr <= 1'b0; + else if ( dinA[1] ) + latsr <= 1'b1; + else if ( clk ) + latsr <= dinA[0]; + + assert_dff lat_test(.clk(clk), .test(doutB), .pat(lat)); + assert_dff latn_test(.clk(clk), .test(doutB1), .pat(latn)); + assert_dff latsr_test(.clk(clk), .test(doutB2), .pat(latsr)); + +endmodule diff --git a/tests/ice40/latches_top.v b/tests/ice40/latches_top.v new file mode 100644 index 000000000..9dc43e4c2 --- /dev/null +++ b/tests/ice40/latches_top.v @@ -0,0 +1,58 @@ +module latchp + ( input d, clk, en, output reg q ); + always @* + if ( en ) + q <= d; +endmodule + +module latchn + ( input d, clk, en, output reg q ); + always @* + if ( !en ) + q <= d; +endmodule + +module latchsr + ( input d, clk, en, clr, pre, output reg q ); + always @* + if ( clr ) + q <= 1'b0; + else if ( pre ) + q <= 1'b1; + else if ( en ) + q <= d; +endmodule + + +module top ( +input clk, +input clr, +input pre, +input a, +output b,b1,b2 +); + + +latchp u_latchp ( + .en (clk ), + .d (a ), + .q (b ) + ); + + +latchn u_latchn ( + .en (clk ), + .d (a ), + .q (b1 ) + ); + + +latchsr u_latchsr ( + .en (clk ), + .clr (clr), + .pre (pre), + .d (a ), + .q (b2 ) + ); + +endmodule diff --git a/tests/ice40/memory.ys b/tests/ice40/memory.ys new file mode 100644 index 000000000..0f030d77d --- /dev/null +++ b/tests/ice40/memory.ys @@ -0,0 +1,7 @@ +proc +memory +equiv_opt -map ../../techlibs/ice40/cells_sim.v synth_ice40 +synth_ice40 +select -assert-count 8 t:SB_DFF +select -assert-count 512 t:SB_DFFE +write_verilog ./temp/memory_synth.v diff --git a/tests/ice40/memory_tb.v b/tests/ice40/memory_tb.v new file mode 100644 index 000000000..5905f3ddd --- /dev/null +++ b/tests/ice40/memory_tb.v @@ -0,0 +1,81 @@ +module testbench; + reg clk; + + initial begin + // $dumpfile("testbench.vcd"); + // $dumpvars(0, testbench); + + #5 clk = 0; + repeat (10000) begin + #5 clk = 1; + #5 clk = 0; + end + + $display("OKAY"); + end + + + reg [7:0] data_a = 0; + reg [5:0] addr_a = 0; + reg we_a = 0; + reg re_a = 1; + wire [7:0] q_a; + reg mem_init = 0; + + reg [7:0] pq_a; + + top uut ( + .data_a(data_a), + .addr_a(addr_a), + .we_a(we_a), + .clk(clk), + .q_a(q_a) + ); + + always @(posedge clk) begin + #3; + data_a <= data_a + 17; + + addr_a <= addr_a + 1; + end + + always @(posedge addr_a) begin + #10; + if(addr_a > 6'h3E) + mem_init <= 1; + end + + always @(posedge clk) begin + //#3; + we_a <= !we_a; + end + + // Declare the RAM variable for check + reg [7:0] ram[63:0]; + + // Port A for check + always @ (posedge clk) + begin + if (we_a) + begin + ram[addr_a] <= data_a; + pq_a <= data_a; + end + pq_a <= ram[addr_a]; + end + + uut_mem_checker port_a_test(.clk(clk), .init(mem_init), .en(!we_a), .A(q_a), .B(pq_a)); + +endmodule + +module uut_mem_checker(input clk, input init, input en, input [7:0] A, input [7:0] B); + always @(posedge clk) + begin + #1; + if (en == 1 & init == 1 & A !== B) + begin + $display("ERROR: ASSERTION FAILED in %m:",$time," ",A," ",B); + $stop; + end + end +endmodule diff --git a/tests/ice40/memory_top.v b/tests/ice40/memory_top.v new file mode 100644 index 000000000..cb7753f7b --- /dev/null +++ b/tests/ice40/memory_top.v @@ -0,0 +1,21 @@ +module top +( + input [7:0] data_a, + input [6:1] addr_a, + input we_a, clk, + output reg [7:0] q_a +); + // Declare the RAM variable + reg [7:0] ram[63:0]; + + // Port A + always @ (posedge clk) + begin + if (we_a) + begin + ram[addr_a] <= data_a; + q_a <= data_a; + end + q_a <= ram[addr_a]; + end +endmodule diff --git a/tests/ice40/mul_pow.ys b/tests/ice40/mul_pow.ys new file mode 100644 index 000000000..486480506 --- /dev/null +++ b/tests/ice40/mul_pow.ys @@ -0,0 +1,6 @@ +equiv_opt -map ../../techlibs/ice40/cells_sim.v synth_ice40 +synth_ice40 +select -assert-count 15 t:SB_LUT4 +select -assert-count 4 t:SB_CARRY +select -assert-count 1 t:$pow +write_verilog ./temp/mul_pow_synth.v diff --git a/tests/ice40/mul_pow_tb.v b/tests/ice40/mul_pow_tb.v new file mode 100644 index 000000000..7e888474f --- /dev/null +++ b/tests/ice40/mul_pow_tb.v @@ -0,0 +1,47 @@ +module testbench; + reg [7:0] in; + + wire [3:0] outA,outB; + wire [3:0] poutA,poutB; + + initial begin + // $dumpfile("testbench.vcd"); + // $dumpvars(0, testbench); + + #5 in = 0; + repeat (10000) begin + #5 in = in + 1; + end + + $display("OKAY"); + end + + top uut ( + .x(in[3:0]), + .y(in[7:4]), + .A(outA), + .B(outB) + ); + + + assign poutA = in[3:0] * in[7:4]; + assign poutB = in[3:0] ** in[7:4]; + + check_comb mul_test(outA, poutA); + check_comb pow_test(outB, poutB); + assert_comb pow2_test(outB[2], poutB[2]); + +endmodule + +module check_comb(input [3:0] test, input [3:0] pat); + always @* + begin + #1; + if (test !== pat) + begin + $display("ERROR: ASSERTION FAILED in %m:",$time," ",test," ",pat); + $stop; + end + end +endmodule + diff --git a/tests/ice40/mul_pow_top.v b/tests/ice40/mul_pow_top.v new file mode 100644 index 000000000..6c256d96b --- /dev/null +++ b/tests/ice40/mul_pow_top.v @@ -0,0 +1,13 @@ +module top +( + input [3:0] x, + input [3:0] y, + + output [3:0] A, + output [3:0] B + ); + +assign A = x * y; +assign B = x ** y; + +endmodule diff --git a/tests/ice40/mux.ys b/tests/ice40/mux.ys new file mode 100644 index 000000000..5ae5a1f33 --- /dev/null +++ b/tests/ice40/mux.ys @@ -0,0 +1,5 @@ +equiv_opt -map ../../techlibs/ice40/cells_sim.v synth_ice40 +synth_ice40 +select -assert-count 20 t:SB_LUT4 +select -assert-count 1 t:SB_CARRY +write_verilog ./temp/mux_synth.v diff --git a/tests/ice40/mux_tb.v b/tests/ice40/mux_tb.v new file mode 100644 index 000000000..2b2da25e9 --- /dev/null +++ b/tests/ice40/mux_tb.v @@ -0,0 +1,43 @@ +module testbench; + reg clk; + + initial begin + // $dumpfile("testbench.vcd"); + // $dumpvars(0, testbench); + + #5 clk = 0; + repeat (10000) begin + #5 clk = 1; + #5 clk = 0; + end + + $display("OKAY"); + end + + + reg [15:0] D = 1; + reg [3:0] S = 0; + wire M2,M4,M8,M16; + + top uut ( + .S (S ), + .D (D ), + .M2 (M2 ), + .M4 (M4 ), + .M8 (M8 ), + .M16 (M16 ) + ); + + always @(posedge clk) begin + //#3; + D <= {D[14:0],D[15]}; + //D <= D <<< 1; + S <= S + 1; + end + + assert_tri m2_test(.en(clk), .A(D[0]|D[1]), .B(M2)); + assert_tri m4_test(.en(clk), .A(D[0]|D[1]|D[2]|D[3]), .B(M4)); + assert_tri m8_test(.en(clk), .A(!S[3]), .B(M8)); + assert_tri m16_test(.en(clk), .A(1'b1), .B(M16)); + +endmodule diff --git a/tests/ice40/mux_top.v b/tests/ice40/mux_top.v new file mode 100644 index 000000000..0814b733e --- /dev/null +++ b/tests/ice40/mux_top.v @@ -0,0 +1,100 @@ +module mux2 (S,A,B,Y); + input S; + input A,B; + output reg Y; + + always @(*) + Y = (S)? B : A; +endmodule + +module mux4 ( S, D, Y ); + +input[1:0] S; +input[3:0] D; +output Y; + +reg Y; +wire[1:0] S; +wire[3:0] D; + +always @* +begin + case( S ) + 0 : Y = D[0]; + 1 : Y = D[1]; + 2 : Y = D[2]; + 3 : Y = D[3]; + endcase +end + +endmodule + +module mux8 ( S, D, Y ); + +input[2:0] S; +input[7:0] D; +output Y; + +reg Y; +wire[2:0] S; +wire[7:0] D; + +always @* +begin + case( S ) + 0 : Y = D[0]; + 1 : Y = D[1]; + 2 : Y = D[2]; + 3 : Y = D[3]; + 4 : Y = D[4]; + 5 : Y = D[5]; + 6 : Y = D[6]; + 7 : Y = D[7]; + endcase +end + +endmodule + +module mux16 (D, S, Y); + input [15:0] D; + input [3:0] S; + output Y; + +assign Y = D[S]; + +endmodule + + +module top ( +input [3:0] S, +input [15:0] D, +output M2,M4,M8,M16 +); + +mux2 u_mux2 ( + .S (S[0]), + .A (D[0]), + .B (D[1]), + .Y (M2) + ); + + +mux4 u_mux4 ( + .S (S[1:0]), + .D (D[3:0]), + .Y (M4) + ); + +mux8 u_mux8 ( + .S (S[2:0]), + .D (D[7:0]), + .Y (M8) + ); + +mux16 u_mux16 ( + .S (S[3:0]), + .D (D[15:0]), + .Y (M16) + ); + +endmodule diff --git a/tests/ice40/run-test.sh b/tests/ice40/run-test.sh new file mode 100755 index 000000000..e839aa9f5 --- /dev/null +++ b/tests/ice40/run-test.sh @@ -0,0 +1,21 @@ +#!/bin/bash +set -e +if [ -f "../../../../../techlibs/common/simcells.v" ]; then + COMMON_PREFIX=../../../../../techlibs/common + TECHLIBS_PREFIX=../../../../../techlibs +else + COMMON_PREFIX=/usr/local/share/yosys + TECHLIBS_PREFIX=/usr/local/share/yosys +fi +for x in *_top.v; do + echo "Running $x.." + ../../yosys -q -s ${x%_top.v}.ys -l ./temp/${x%.v}.log $x + echo "Simulating $x.." + iverilog -o ./temp/${x%_top.v}_testbench ${x%_top.v}_tb.v ./temp/${x%_top.v}_synth.v common.v $COMMON_PREFIX/simcells.v $TECHLIBS_PREFIX/ice40/cells_sim.v + if ! vvp -N ./temp/${x%_top.v}_testbench > ./temp/${x%_top.v}_testbench.log 2>&1; then + grep 'ERROR' ./temp/${x%_top.v}_testbench.log + exit 0 + elif grep 'ERROR' ./temp/${x%_top.v}_testbench.log || ! grep 'OKAY' ./temp/${x%_top.v}_testbench.log; then + exit 0 + fi +done diff --git a/tests/ice40/tribuf.ys b/tests/ice40/tribuf.ys new file mode 100644 index 000000000..40ded734d --- /dev/null +++ b/tests/ice40/tribuf.ys @@ -0,0 +1,6 @@ +equiv_opt -map ../../techlibs/ice40/cells_sim.v synth_ice40 +synth_ice40 +select -assert-count 1 t:SB_LUT4 +select -assert-count 1 t:SB_CARRY +select -assert-count 1 t:$_TBUF_ +write_verilog ./temp/tribuf_synth.v diff --git a/tests/ice40/tribuf_tb.v b/tests/ice40/tribuf_tb.v new file mode 100644 index 000000000..16871b7b2 --- /dev/null +++ b/tests/ice40/tribuf_tb.v @@ -0,0 +1,34 @@ +module testbench; + reg en; + + initial begin + // $dumpfile("testbench.vcd"); + // $dumpvars(0, testbench); + + #5 en = 0; + repeat (10000) begin + #5 en = 1; + #5 en = 0; + end + + $display("OKAY"); + end + + + reg dinA = 0; + wire doutB; + + top uut ( + .en (en ), + .a (dinA ), + .b (doutB ) + ); + + always @(posedge en) begin + #3; + dinA <= !dinA; + end + + assert_tri b_test(.en(en), .A(dinA), .B(doutB)); + +endmodule diff --git a/tests/ice40/tribuf_top.v b/tests/ice40/tribuf_top.v new file mode 100644 index 000000000..b2b5e37d6 --- /dev/null +++ b/tests/ice40/tribuf_top.v @@ -0,0 +1,23 @@ +module tristate (en, i, o); + input en; + input i; + output reg o; + + always @(en or i) + o <= (en)? i : 1'bZ; +endmodule + + +module top ( +input en, +input a, +output b +); + +tristate u_tri ( + .en (en ), + .i (a ), + .o (b ) + ); + +endmodule