From: Chia-I Wu Date: Sun, 21 Sep 2014 14:33:50 +0000 (+0800) Subject: ilo: support prim queries in ilo_3d_pipeline_emit_query() X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=154972700d54f83827dbccad1ef09077a63c8a59;p=mesa.git ilo: support prim queries in ilo_3d_pipeline_emit_query() Add support for PIPE_QUERY_PRIMITIVES_GENERATED and PIPE_QUERY_PRIMITIVES_EMITTED in ilo_3d_pipeline_emit_query(). Signed-off-by: Chia-I Wu --- diff --git a/src/gallium/drivers/ilo/ilo_3d_pipeline_gen6.c b/src/gallium/drivers/ilo/ilo_3d_pipeline_gen6.c index ee2cba18ab5..718afe71219 100644 --- a/src/gallium/drivers/ilo/ilo_3d_pipeline_gen6.c +++ b/src/gallium/drivers/ilo/ilo_3d_pipeline_gen6.c @@ -1482,6 +1482,14 @@ ilo_3d_pipeline_emit_query_gen6(struct ilo_3d_pipeline *p, (ilo_dev_gen(p->dev) >= ILO_GEN(7)) ? GEN7_REG_DS_INVOCATION_COUNT : 0, 0, }; + const uint32_t primitives_generated_reg = + (ilo_dev_gen(p->dev) >= ILO_GEN(7) && q->index > 0) ? + GEN7_REG_SO_PRIM_STORAGE_NEEDED(q->index) : + GEN6_REG_CL_INVOCATION_COUNT; + const uint32_t primitives_emitted_reg = + (ilo_dev_gen(p->dev) >= ILO_GEN(7)) ? + GEN7_REG_SO_NUM_PRIMS_WRITTEN(q->index) : + GEN6_REG_SO_NUM_PRIMS_WRITTEN; const uint32_t *regs; int reg_count = 0, i; @@ -1506,6 +1514,14 @@ ilo_3d_pipeline_emit_query_gen6(struct ilo_3d_pipeline *p, GEN6_PIPE_CONTROL_WRITE_TIMESTAMP, q->bo, offset, true); break; + case PIPE_QUERY_PRIMITIVES_GENERATED: + regs = &primitives_generated_reg; + reg_count = 1; + break; + case PIPE_QUERY_PRIMITIVES_EMITTED: + regs = &primitives_emitted_reg; + reg_count = 1; + break; case PIPE_QUERY_PIPELINE_STATISTICS: regs = pipeline_statistics_regs; reg_count = Elements(pipeline_statistics_regs); @@ -1880,6 +1896,14 @@ gen6_pipeline_estimate_query_size(const struct ilo_3d_pipeline *p, if (ilo_dev_gen(p->dev) == ILO_GEN(6)) size *= 2; break; + case PIPE_QUERY_PRIMITIVES_GENERATED: + case PIPE_QUERY_PRIMITIVES_EMITTED: + size = GEN6_PIPE_CONTROL__SIZE; + if (ilo_dev_gen(p->dev) == ILO_GEN(6)) + size *= 3; + + size += GEN6_MI_STORE_REGISTER_MEM__SIZE * 2; + break; case PIPE_QUERY_PIPELINE_STATISTICS: if (ilo_dev_gen(p->dev) >= ILO_GEN(7)) { const int num_regs = 10;