From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Fri, 27 Oct 2023 10:24:10 +0000 (+0100)
Subject: whitespace
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=154ba6ea9ceb27519c78db5b100f37ad632f3699;p=openpower-isa.git

whitespace
---

diff --git a/openpower/isa/pifixedloadshift.mdwn b/openpower/isa/pifixedloadshift.mdwn
index 98d7edd6..b383a967 100644
--- a/openpower/isa/pifixedloadshift.mdwn
+++ b/openpower/isa/pifixedloadshift.mdwn
@@ -23,6 +23,7 @@ Pseudo-code:
 Description:
 
     Let the effective address (EA) be register RA.
+
     The byte in storage addressed by EA is loaded into RT[56:63]. 
     RT[0:55] are set to 0.
 
@@ -75,6 +76,7 @@ Pseudo-code:
 Description:
 
     Let the effective address (EA) be the register RA.
+
     The halfword in storage addressed by EA is loaded into RT[48:63].
     RT[0:47] are filled with a copy of bit 0 of the loaded halfword.
 
@@ -101,6 +103,7 @@ Pseudo-code:
 Description:
 
     Let the effective address (EA) be the register RA.
+
     The halfword in storage addressed by EA is loaded into RT[48:63].
     RT[0:47] are filled with a copy of bit 0 of the loaded halfword.
 
@@ -127,6 +130,7 @@ Pseudo-code:
 Description:
 
     Let the effective address (EA) be the register RA.
+
     The halfword in storage addressed by EA is loaded into RT[48:63].
     RT[0:47] are filled with a copy of bit 0 of the loaded halfword.
 
@@ -153,6 +157,7 @@ Pseudo-code:
 Description:
 
     Let the effective address (EA) be the register RA.
+
     The word in storage addressed by EA is loaded into RT[32:63].
     RT[0:31] are filled with a copy of bit 0 of the loaded word.
 
@@ -179,8 +184,8 @@ Pseudo-code:
 Description:
 
     Let the effective address (EA) be the register RA.
-    The doubleword in storage addressed by EA is loaded
-    into RT.
+
+    The doubleword in storage addressed by EA is loaded into RT.
 
     The sum (RA) + (RB) is placed into register RA.