From: Eddie Hung <eddie@fpgeh.com>
Date: Wed, 14 Aug 2019 23:26:24 +0000 (-0700)
Subject: AND with an inverted input, causes X{,N}OR output to be inverted too
X-Git-Tag: working-ls180~1143^2~1
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=1551e14d2d688982f22f416a55a3212796a82421;p=yosys.git

AND with an inverted input, causes X{,N}OR output to be inverted too
---

diff --git a/passes/techmap/extract_fa.cc b/passes/techmap/extract_fa.cc
index b541ceb6b..8f195a90a 100644
--- a/passes/techmap/extract_fa.cc
+++ b/passes/techmap/extract_fa.cc
@@ -513,13 +513,13 @@ struct ExtractFaWorker
 				}
 
 				if (func2.at(key).count(xor2_func)) {
-					SigBit YY = invert_xy ? module->NotGate(NEW_ID, Y) : Y;
+					SigBit YY = invert_xy || (f2i.inv_a && !f2i.inv_b) || (!f2i.inv_a && f2i.inv_b) ? module->NotGate(NEW_ID, Y) : Y;
 					for (auto bit : func2.at(key).at(xor2_func))
 						assign_new_driver(bit, YY);
 				}
 
 				if (func2.at(key).count(xnor2_func)) {
-					SigBit YY = invert_xy ? Y : module->NotGate(NEW_ID, Y);
+					SigBit YY = invert_xy || (f2i.inv_a && !f2i.inv_b) || (!f2i.inv_a && f2i.inv_b) ? Y : module->NotGate(NEW_ID, Y);
 					for (auto bit : func2.at(key).at(xnor2_func))
 						assign_new_driver(bit, YY);
 				}