From: lkcl Date: Wed, 16 Dec 2020 09:07:26 +0000 (+0000) Subject: (no commit message) X-Git-Tag: convert-csv-opcode-to-binary~1290 X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=1557523ee93b5696121ccc396db3688ed3146dd4;p=libreriscv.git --- diff --git a/openpower/sv/svp_rewrite/svp64.mdwn b/openpower/sv/svp_rewrite/svp64.mdwn index 18429fa82..d4b56e37a 100644 --- a/openpower/sv/svp_rewrite/svp64.mdwn +++ b/openpower/sv/svp_rewrite/svp64.mdwn @@ -63,7 +63,7 @@ Shows all fields in the Remapped Encoding `RM[0:23]` for all instruction variant note in [[discussion]]: TODO, evaluate if 2nd SUBVL should be added. conclusion: no. 2nd SUBVL makes no sense except for mv, and that is covered by [[mv.vec]] -## R\*_EXTRA Encoding +## R\*_EXTRA2 and R\*_EXTRA3 Encoding (**TODO: 2-bit version of the table, just like in the original SVPrefix. This is important, to save bits on 4-operand instructions such as fmadd**) @@ -73,7 +73,7 @@ In the following table, `` denotes the value of the corresponding register fi 3 bit version -| R\*_EXTRA | Vector/Scalar
Mode | CR Register | Int/FP
Register | +| R\*_EXTRA3 | Vector/Scalar
Mode | CR Register | Int/FP
Register | |-----------|------------------------|---------------|---------------------| | 000 | Scalar | `SVCR_000` | `SV[F]R_00` | | 001 | Scalar | `SVCR_010` | `SV[F]R_01` | @@ -88,7 +88,7 @@ In the following table, `` denotes the value of the corresponding register fi (**TODO, i simply cannot interpret the names, they have absolutely zero meaning to me so i have no idea how to fill in the table. this is a bad sign, indicative that the names have to go, to be replaced by something xlear snd obvious**) -| R\*_EXTRA | Vector/Scalar
Mode | CR Register | Int/FP
Register | +| R\*_EXTRA2 | Vector/Scalar
Mode | CR Register | Int/FP
Register | |-----------|------------------------|---------------|---------------------| | 00 | Scalar | `SVCR_000` | `SV[F]R_00` | | 01 | Scalar | `SVCR_100` | `SV[F]R_10` |