From: Florent Kermarrec <florent@enjoy-digital.fr>
Date: Thu, 19 Jul 2018 10:51:16 +0000 (+0200)
Subject: soc/integration/soc_sdram: add assertion on csr_data_width since BIOS only support... 
X-Git-Tag: 24jan2021_ls180~1666
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=1564b440eb1a993664defbdccddc0a71816fb0c4;p=litex.git

soc/integration/soc_sdram: add assertion on csr_data_width since BIOS only support SDRAM initialization for csr_data_width=8
---

diff --git a/litex/soc/integration/soc_sdram.py b/litex/soc/integration/soc_sdram.py
index 1c9064c2..218ac86b 100644
--- a/litex/soc/integration/soc_sdram.py
+++ b/litex/soc/integration/soc_sdram.py
@@ -37,6 +37,8 @@ class SoCSDRAM(SoCCore):
 
     def __init__(self, platform, clk_freq, l2_size=8192, **kwargs):
         SoCCore.__init__(self, platform, clk_freq, **kwargs)
+        if self.cpu_type is not None and self.csr_data_width != 8:
+             raise NotImplementedError("BIOS supports SDRAM initialization only for csr_data_width=8")
         self.l2_size = l2_size
 
         self._sdram_phy = []