From: Eddie Hung <eddie@fpgeh.com>
Date: Tue, 25 Jun 2019 05:48:49 +0000 (-0700)
Subject: Merge remote-tracking branch 'origin/xaig' into xc7mux
X-Git-Tag: working-ls180~1208^2~81
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=1564eb8b549a0927efa4d2b4cbc479038993024a;p=yosys.git

Merge remote-tracking branch 'origin/xaig' into xc7mux
---

1564eb8b549a0927efa4d2b4cbc479038993024a
diff --cc techlibs/xilinx/cells_sim.v
index 29abc9807,8261286af..c6c49c3cd
--- a/techlibs/xilinx/cells_sim.v
+++ b/techlibs/xilinx/cells_sim.v
@@@ -289,23 -281,7 +289,24 @@@ module FDPE_1 (output reg Q, input C, C
    always @(negedge C, posedge PRE) if (PRE) Q <= 1'b1; else if (CE) Q <= D;
  endmodule
  
 +module RAM32X1D (
 +  output DPO, SPO,
 +  input  D, WCLK, WE,
 +  input  A0, A1, A2, A3, A4,
 +  input  DPRA0, DPRA1, DPRA2, DPRA3, DPRA4,
 +);
 +  parameter INIT = 32'h0;
 +  parameter IS_WCLK_INVERTED = 1'b0;
 +  wire [4:0] a = {A4, A3, A2, A1, A0};
 +  wire [4:0] dpra = {DPRA4, DPRA3, DPRA2, DPRA1, DPRA0};
 +  reg [31:0] mem = INIT;
 +  assign SPO = mem[a];
 +  assign DPO = mem[dpra];
 +  wire clk = WCLK ^ IS_WCLK_INVERTED;
 +  always @(posedge clk) if (WE) mem[a] <= D;
 +endmodule
 +
+ (* abc_box_id = 4, abc_scc_break="D" *)
  module RAM64X1D (
    output DPO, SPO,
    input  D, WCLK, WE,