From: lkcl <lkcl@web>
Date: Thu, 28 Jan 2021 00:16:49 +0000 (+0000)
Subject: (no commit message)
X-Git-Tag: convert-csv-opcode-to-binary~287
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=15812bfd313b351110df9484a9d57d5e34ccd236;p=libreriscv.git

---

diff --git a/openpower/sv/bitmanip.mdwn b/openpower/sv/bitmanip.mdwn
index 46b7b5287..8f34351d4 100644
--- a/openpower/sv/bitmanip.mdwn
+++ b/openpower/sv/bitmanip.mdwn
@@ -148,24 +148,11 @@ a 4 operand variant which becomes more along the lines of an FPGA:
         idx = RT[i] << 2 | RA[i] << 1 | RB[i]
         RT[i] = (RC & (1<<idx)) != 0
 
-mode (2 bit) may be used to do inversion of ordering, similar to carryless mul.
+mode (2 bit) may be used to do inversion of ordering, similar to carryless mul,
+3 modes.
 
 also, another possible variant involving swizzle and vec4:
 
-    for i in range(8):
-        idx = RA.x[i] << 2 | RA.y[i] << 1 | RA.z[i]
-        RT[i] = (RA.w[i] & (1<<idx)) != 0
-
-| 0.5|6.10|11.15| 16.23 |24.27 | 28.30 |31|
-| -- | -- | --- | ----- | ---- | ----- |--|
-| NN | RT | RA  | xyzw  | mask | 01 1  |1 |
-
-    for i in range(8):
-        idx = RA.x[i] << 2 | RA.y[i] << 1 | RA.z[i]   
-        res = (RA.w[i] & (1<<idx)) != 0
-        for j in range(4):
-             if mask[j]: RT[i+j*8] = res
-
 | 0.5|6.10|11.15| 16.23 |24.27 | 28.30 |31|
 | -- | -- | --- | ----- | ---- | ----- |--|
 | NN | RT | RA  | imm   | mask | 101   |1 |
@@ -438,10 +425,18 @@ realistically with the degree also needing to be an immediate it should be broug
 
 | 0.5|6.10|11.15|16.20|21.25| 26..30  |31|
 | -- | -- | --- | --- | --- | ------- |--|
-| NN | RS | RA  | RB  | deg |         |  |
+| NN | RS | RA  | RB  | deg | 00  011 |Rc|
 
 where the SimpleV variant may override RS-as-src differently from RS-as-dest
 
+GF add
+
+    RS = GFADD(RS, RA|0, gfdegree, modulo=RB)
+
+| 0.5|6.10|11.15|16.20|21.25| 26..30  |31|
+| -- | -- | --- | --- | --- | ------- |--|
+| NN | RS | RA  | RB  | deg | 01  011 |Rc|
+
 
 ```
 from functools import reduce