From: Eddie Hung <eddie@fpgeh.com>
Date: Tue, 25 Jun 2019 06:05:28 +0000 (-0700)
Subject: Realistic delays for RAM32X1D too
X-Git-Tag: working-ls180~1208^2~78
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=158325956e6bf711137e6198fb88e95a1e6250b9;p=yosys.git

Realistic delays for RAM32X1D too
---

diff --git a/techlibs/xilinx/abc_xc7.box b/techlibs/xilinx/abc_xc7.box
index c95ba4969..67d1ffb1e 100644
--- a/techlibs/xilinx/abc_xc7.box
+++ b/techlibs/xilinx/abc_xc7.box
@@ -39,8 +39,8 @@ CARRY4 3 1 10 8
 # Inputs: A0 A1 A2 A3 A4 D DPRA0 DPRA1 DPRA2 DPRA3 DPRA4 WCLK WE
 # Outputs: DPO SPO
 RAM32X1D 4 0 13 2
--   -   -   -   -   - 124 124 124 124 124 - -
-124 124 124 124 124 - -   -   -   -   -   - -
+-   -   -   -   -   - 631 472 407 238 127 - -
+631 472 407 238 127 - -   -   -   -   -   - -
 
 # SLICEM/A6LUT
 # Inputs: A0 A1 A2 A3 A4 A5 D DPRA0 DPRA1 DPRA2 DPRA3 DPRA4 DPRA5 WCLK WE