From: Dmitry Selyutin Date: Fri, 9 Sep 2022 14:30:28 +0000 (+0300) Subject: minor_30: fix rldicl form X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=159f0259354316e55b18c3939e73f3efbea1800e;p=openpower-isa.git minor_30: fix rldicl form --- diff --git a/openpower/isatables/minor_30.csv b/openpower/isatables/minor_30.csv index 3a598373..0c41e53b 100644 --- a/openpower/isatables/minor_30.csv +++ b/openpower/isatables/minor_30.csv @@ -2,7 +2,7 @@ # derived from microwatt decode1.vhdl, with thanks and gratitude (IBM, OPF) opcode,unit,internal op,in1,in2,in3,out,CR in,CR out,inv A,inv out,cry in,cry out,ldst len,BR,sgn ext,upd,rsrv,32b,sgn,rc,lk,sgl pipe,comment,form,CONDITIONS 010-,SHIFT_ROT,OP_RLC,NONE,CONST_SH,RS,RA,NONE,CR0,0,0,ZERO,0,NONE,0,0,0,0,0,0,RC_ONLY,0,0,rldic,MD, -000-,SHIFT_ROT,OP_RLCL,NONE,CONST_SH,RS,RA,NONE,CR0,0,0,ZERO,0,NONE,0,0,0,0,0,0,RC_ONLY,0,0,rldicl,MDS, +000-,SHIFT_ROT,OP_RLCL,NONE,CONST_SH,RS,RA,NONE,CR0,0,0,ZERO,0,NONE,0,0,0,0,0,0,RC_ONLY,0,0,rldicl,MD, 001-,SHIFT_ROT,OP_RLCR,NONE,CONST_SH,RS,RA,NONE,CR0,0,0,ZERO,0,NONE,0,0,0,0,0,0,RC_ONLY,0,0,rldicr,MD, 011-,SHIFT_ROT,OP_RLC,RA,CONST_SH,RS,RA,NONE,CR0,0,0,ZERO,0,NONE,0,0,0,0,0,0,RC_ONLY,0,0,rldimi,MD, 1000,SHIFT_ROT,OP_RLCL,NONE,RB,RS,RA,NONE,CR0,0,0,ZERO,0,NONE,0,0,0,0,0,0,RC_ONLY,0,0,rldcl,MDS,