From: Clifford Wolf <clifford@clifford.at>
Date: Fri, 23 Oct 2015 13:26:58 +0000 (+0200)
Subject: Also merge $equiv cells in equiv_struct
X-Git-Tag: yosys-0.6~97
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=15a67392f10263b59d34021b08fbb48685d7ec16;p=yosys.git

Also merge $equiv cells in equiv_struct
---

diff --git a/passes/equiv/equiv_struct.cc b/passes/equiv/equiv_struct.cc
index ff844ea21..c509e2556 100644
--- a/passes/equiv/equiv_struct.cc
+++ b/passes/equiv/equiv_struct.cc
@@ -119,6 +119,7 @@ struct EquivStructWorker
 		for (auto cell : module->selected_cells())
 			if (cell->type == "$equiv") {
 				equiv_bits.add(sigmap(cell->getPort("\\A")), sigmap(cell->getPort("\\B")));
+				cells_by_type[cell->type].insert(cell->name);
 			} else
 			if (module->design->selected(module, cell)) {
 				if (mode_icells || module->design->module(cell->type))