From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Sat, 8 Jun 2019 11:59:54 +0000 (+0100)
Subject: whoops use reduce(or_) not bool to merge bitwise src in dep cells
X-Git-Tag: div_pipeline~1875
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=15b5af5e115f4a9ddd248d494aadf20f4b85fe3b;p=soc.git

whoops use reduce(or_) not bool to merge bitwise src in dep cells
---

diff --git a/src/scoreboard/dependence_cell.py b/src/scoreboard/dependence_cell.py
index 6e60d1d8..32c568bf 100644
--- a/src/scoreboard/dependence_cell.py
+++ b/src/scoreboard/dependence_cell.py
@@ -2,7 +2,8 @@ from nmigen.compat.sim import run_simulation
 from nmigen.cli import verilog, rtlil
 from nmigen import Module, Signal, Elaboratable, Array, Cat, Repl
 from nmutil.latch import SRLatch
-
+from functools import reduce
+from operator import or_
 
 class DependencyRow(Elaboratable):
     """ implements 11.4.7 mitch alsup dependence cell, p27
@@ -102,7 +103,7 @@ class DependencyRow(Elaboratable):
         src_q = []
         for i in range(self.n_src):
             src_q.append(src_c[i].qlq)
-        m.d.comb += self.v_rd_rsel_o.eq(Cat(*src_q).bool())
+        m.d.comb += self.v_rd_rsel_o.eq(reduce(or_, src_q))
         m.d.comb += self.v_wr_rsel_o.eq(dest_c.qlq)
 
         return m