From: lkcl Date: Wed, 26 Apr 2023 05:06:43 +0000 (+0100) Subject: (no commit message) X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=15c68ff1a92a386a3152682de10acfe7bc1a6cc7;p=libreriscv.git --- diff --git a/openpower/sv/cr_int_predication.mdwn b/openpower/sv/cr_int_predication.mdwn index 38733a22a..f2c510202 100644 --- a/openpower/sv/cr_int_predication.mdwn +++ b/openpower/sv/cr_int_predication.mdwn @@ -1,5 +1,6 @@ # New instructions for CR/INT predication + See: * main bugreport for crweirds @@ -8,6 +9,7 @@ See: * * * [[discussion]] + ## crrweird @@ -23,12 +25,12 @@ CW2-Form * crrweird. RT,BFA,M,fmsk,fmap (Rc=1) ``` - creg = CR[4*BFA+32:4*BFA+35] - n = (¬fmap ^ creg) & fmsk - result = (n != 0) if M else (n == fmsk) - RT = [0] * 63 || result - If Rc: - CR0 = analyse(RT) + creg <- CR[4*BFA+32:4*BFA+35] + n <- (¬fmap ^ creg) & fmsk + result <- (n != 0) if M else (n == fmsk) + RT <- [0] * 63 || result + if Rc then + CR0 <- analyse(RT) ``` When used with SVP64 Prefixing this is a [[sv/normal]]