From: lkcl <lkcl@web>
Date: Fri, 4 Jun 2021 00:44:39 +0000 (+0100)
Subject: (no commit message)
X-Git-Tag: DRAFT_SVP64_0_1~822
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=15d027866462b0e2468f4e3c1865035704cdb6ff;p=libreriscv.git

---

diff --git a/openpower/sv/int_fp_mv.mdwn b/openpower/sv/int_fp_mv.mdwn
index 8e86c8f10..2354e3b5b 100644
--- a/openpower/sv/int_fp_mv.mdwn
+++ b/openpower/sv/int_fp_mv.mdwn
@@ -172,7 +172,16 @@ move a 32-bit float from a GPR to a FPR, just copying bits. Converts the
 
 TODO: Rc=1 variants?
 
-TODO: clear statement on evaluation as to whethrer exceptions or flags raised as part of the **FP** conversion (not the int bitcopy part, the converdion part.  the semantics should really be the same as frsp)
+TODO: clear statement on evaluation as to whethrer exceptions or flags raised as part of the **FP** conversion (not the int bitcopy part, the conversion part.  the semantics should really be the same as frsp)
+
+v3.0C section 4.6.1 states:
+
+FPRF is set to the class and sign of the result, except for Invalid Operation Exceptions when VE=1.
+
+    Special Registers Altered:
+      FPRF FR FI
+      FX OX UX XX VXSNAN
+      CR1 (if Rc=1)
 
 ### Float load immediate (kinda a variant of `fmvfg`)