From: Gabe Black <gblack@eecs.umich.edu>
Date: Thu, 28 Dec 2006 19:29:17 +0000 (-0500)
Subject: Make sure the value of PC is actually updated now that the instruction target isn... 
X-Git-Tag: m5_2.0_beta3~259
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=15df0a27bbf1409f974edbc1f5ffbdf2715ec4f9;p=gem5.git

Make sure the value of PC is actually updated now that the instruction target isn't set explicitly.

--HG--
extra : convert_revision : 4c00a219ac1d82abea78e4e8d70f529a435fdfe2
---

diff --git a/src/cpu/o3/bpred_unit_impl.hh b/src/cpu/o3/bpred_unit_impl.hh
index dbc603082..84c50b4da 100644
--- a/src/cpu/o3/bpred_unit_impl.hh
+++ b/src/cpu/o3/bpred_unit_impl.hh
@@ -149,7 +149,7 @@ BPredUnit<Impl>::predict(DynInstPtr &inst, Addr &PC, unsigned tid)
     using TheISA::MachInst;
 
     bool pred_taken = false;
-    Addr target;
+    Addr target = PC;
 
     ++lookups;
 
@@ -233,6 +233,8 @@ BPredUnit<Impl>::predict(DynInstPtr &inst, Addr &PC, unsigned tid)
         }
     }
 
+    PC = target;
+
     predHist[tid].push_front(predict_record);
 
     DPRINTF(Fetch, "[tid:%i]: predHist.size(): %i\n", tid, predHist[tid].size());