From: lkcl <lkcl@web>
Date: Mon, 24 Jun 2019 01:07:48 +0000 (+0100)
Subject: (no commit message)
X-Git-Tag: convert-csv-opcode-to-binary~4492
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=1615e348ad28b70bd65a53b04fc8f0e05868fb32;p=libreriscv.git

---

diff --git a/simple_v_extension/specification.mdwn b/simple_v_extension/specification.mdwn
index 89b6bc082..e71414f4a 100644
--- a/simple_v_extension/specification.mdwn
+++ b/simple_v_extension/specification.mdwn
@@ -2532,3 +2532,39 @@ Could the 8 bit Register VLIW format use regnum<<1 instead, only accessing regs
 
 TODO evaluate strncpy and strlen
 https://groups.google.com/forum/m/#!msg/comp.arch/bGBeaNjAKvc/_vbqyxTUAQAJ
+
+strncpy: 
+    mv a3, a0               # Copy dst 
+loop: 
+    setvli x0, a2, vint8    # Vectors of bytes. 
+    vlbff.v v1, (a1)        # Get src bytes 
+    vseq.vi v0, v1, 0       # Flag zero bytes 
+    vmfirst a4, v0          # Zero found? 
+    vmsif.v v0, v0          # Set mask up to and including zero byte. 
+    vsb.v v1, (a3), v0.t    # Write out bytes 
+    bgez a4, exit           # Done 
+    csrr t1, vl             # Get number of bytes fetched 
+    add a1, a1, t1          # Bump src pointer 
+    sub a2, a2, t1          # Decrement count. 
+    add a3, a3, t1          # Bump dst pointer 
+    bnez a2, loop           # Anymore? 
+
+exit: 
+    ret 
+
+
+
+    mv a3, a0             # Save start 
+loop: 
+    setvli a1, x0, vint8  # byte vec, x0 (Zero reg) => use max hardware len 
+    vldbff.v v1, (a3)     # Get bytes 
+    csrr a1, vl           # Get bytes actually read e.g. if fault 
+    vseq.vi v0, v1, 0     # Set v0[i] where v1[i] = 0 
+    add a3, a3, a1        # Bump pointer 
+    vmfirst a2, v0        # Find first set bit in mask, returns -1 if none 
+    bltz a2, loop         # Not found? 
+
+    add a0, a0, a1        # Sum start + bump 
+    add a3, a3, a2        # Add index of zero byte 
+    sub a0, a3, a0        # Subtract start address+bump 
+    ret