From: Jonathan Marek <jonathan@marek.ca>
Date: Tue, 16 Jun 2020 22:54:47 +0000 (-0400)
Subject: turnip: set VFD_INDEX_OFFSET in 3D clear/blit path
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=1622787ee4de8785d042e16ce91f027870f87830;p=mesa.git

turnip: set VFD_INDEX_OFFSET in 3D clear/blit path

This was missing an causing flakes when used after a test that set it to
a non-zero value.

Signed-off-by: Jonathan Marek <jonathan@marek.ca>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5509>
---

diff --git a/.gitlab-ci/deqp-freedreno-a630-skips.txt b/.gitlab-ci/deqp-freedreno-a630-skips.txt
index 6bb49cffe2a..6007aeb4e20 100644
--- a/.gitlab-ci/deqp-freedreno-a630-skips.txt
+++ b/.gitlab-ci/deqp-freedreno-a630-skips.txt
@@ -63,8 +63,6 @@ dEQP-GLES3.functional.transform_feedback.array_element.interleaved.triangles.low
 dEQP-GLES3.functional.transform_feedback.array_element.separate.triangles.lowp_mat2x4
 
 # Non-sysmem flakes
-dEQP-VK.pipeline.stencil.format.d24_unorm_s8_uint.states.fail_incc.pass_repl.dfail_decw.comp_not_equal
-dEQP-VK.pipeline.stencil.nocolor.format.d24_unorm_s8_uint.states.fail_repl.pass_decc.dfail_repl.comp_always
 dEQP-VK.pipeline.spec_constant.compute.composite.matrix.mat3x2
 
 # Sysmem flake: this one is fairly frequent, but if you enable it then
diff --git a/src/freedreno/vulkan/tu_clear_blit.c b/src/freedreno/vulkan/tu_clear_blit.c
index e4c573142b1..34591443ae5 100644
--- a/src/freedreno/vulkan/tu_clear_blit.c
+++ b/src/freedreno/vulkan/tu_clear_blit.c
@@ -483,8 +483,8 @@ r2d_run(struct tu_cmd_buffer *cmd, struct tu_cs *cs)
 /* r3d_ = shader path operations */
 
 static void
-r3d_pipeline(struct tu_cmd_buffer *cmd, struct tu_cs *cs, bool blit, uint32_t num_rts,
-             bool layered_clear)
+r3d_common(struct tu_cmd_buffer *cmd, struct tu_cs *cs, bool blit, uint32_t num_rts,
+           bool layered_clear)
 {
    struct ir3_shader dummy_shader = {};
 
@@ -700,6 +700,10 @@ r3d_pipeline(struct tu_cmd_buffer *cmd, struct tu_cs *cs, bool blit, uint32_t nu
    tu_cs_emit_regs(cs,
                    A6XX_GRAS_SC_SCREEN_SCISSOR_TL_0(.x = 0, .y = 0),
                    A6XX_GRAS_SC_SCREEN_SCISSOR_BR_0(.x = 0x7fff, .y = 0x7fff));
+
+   tu_cs_emit_regs(cs,
+                   A6XX_VFD_INDEX_OFFSET(),
+                   A6XX_VFD_INSTANCE_START_OFFSET());
 }
 
 static void
@@ -932,7 +936,7 @@ r3d_setup(struct tu_cmd_buffer *cmd,
    tu_cs_emit_regs(cs, A6XX_GRAS_BIN_CONTROL(.dword = 0xc00000));
    tu_cs_emit_regs(cs, A6XX_RB_BIN_CONTROL(.dword = 0xc00000));
 
-   r3d_pipeline(cmd, cs, !clear, clear ? 1 : 0, false);
+   r3d_common(cmd, cs, !clear, clear ? 1 : 0, false);
 
    tu_cs_emit_pkt4(cs, REG_A6XX_SP_FS_OUTPUT_CNTL0, 2);
    tu_cs_emit(cs, A6XX_SP_FS_OUTPUT_CNTL0_DEPTH_REGID(0xfc) |
@@ -2092,7 +2096,7 @@ tu_clear_sysmem_attachments(struct tu_cmd_buffer *cmd,
          layered_clear = true;
    }
 
-   r3d_pipeline(cmd, cs, false, num_rts, layered_clear);
+   r3d_common(cmd, cs, false, num_rts, layered_clear);
 
    tu_cs_emit_regs(cs,
                    A6XX_SP_FS_RENDER_COMPONENTS(.dword = clear_components));