From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Sat, 23 Jun 2018 08:58:15 +0000 (+0100)
Subject: update
X-Git-Tag: convert-csv-opcode-to-binary~5118
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=162e5c1feb9b176163e72972c4bf3b073a6f0754;p=libreriscv.git

update
---

diff --git a/simple_v_extension/simple_v_chennai_2018.tex b/simple_v_extension/simple_v_chennai_2018.tex
index 46b8b5dc0..9b0207ecd 100644
--- a/simple_v_extension/simple_v_chennai_2018.tex
+++ b/simple_v_extension/simple_v_chennai_2018.tex
@@ -59,6 +59,8 @@
 
  \begin{itemize}
    \item Effectively a variant of SIMD / SIMT (arbitrary length)\vspace{4pt}
+   \item Fascinatingly, despite being a SIMD-variant, RVV only has
+         O(N) opcode proliferation! (extremely well designed)
    \item Extremely powerful (extensible to 256 registers)\vspace{4pt}
    \item Supports polymorphism, several datatypes (inc. FP16)\vspace{4pt}
    \item Requires a separate Register File (32 w/ext to 256)\vspace{4pt}
@@ -69,8 +71,6 @@
    \item 98 percent opcode duplication with rest of RV
    \item Extending RVV requires customisation not just of h/w:\\
 	     gcc, binutils also need customisation (and maintenance)
-   \item Fascinatingly, despite being a SIMD-variant, RVV only has
-         O(N) opcode proliferation! (extremely well designed)
   \end{itemize}
 }