From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Thu, 18 Oct 2018 22:30:04 +0000 (+0100)
Subject: div, fcvt
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=1634b06f6ea16332dec7c03363cdba5ef103af84;p=riscv-isa-sim.git

div, fcvt
---

diff --git a/riscv/insns/divw.h b/riscv/insns/divw.h
index f8b4785..2f172ea 100644
--- a/riscv/insns/divw.h
+++ b/riscv/insns/divw.h
@@ -1,8 +1,8 @@
 require_extension('M');
 require_rv64;
-sreg_t lhs = sext32(RS1);
-sreg_t rhs = sext32(RS2);
-if(rhs == 0)
+sv_sreg_t lhs = sext32(RS1);
+sv_sreg_t rhs = sext32(RS2);
+if(rv_eq(rhs, sv_reg_t(0)))
   WRITE_RD(UINT64_MAX);
 else
   WRITE_RD(sext32(rv_div(lhs, rhs)));
diff --git a/riscv/insns/fcvt_d_w.h b/riscv/insns/fcvt_d_w.h
index 4c4861c..76ec6e6 100644
--- a/riscv/insns/fcvt_d_w.h
+++ b/riscv/insns/fcvt_d_w.h
@@ -1,5 +1,5 @@
 require_extension('D');
 require_fp;
 softfloat_roundingMode = RM;
-WRITE_FRD(i32_to_f64((int32_t)RS1));
+WRITE_FRD(i32_to_f64(sv_reg_int32(RS1)));
 set_fp_exceptions;
diff --git a/riscv/insns/fcvt_d_wu.h b/riscv/insns/fcvt_d_wu.h
index 1dbf218..afa6d72 100644
--- a/riscv/insns/fcvt_d_wu.h
+++ b/riscv/insns/fcvt_d_wu.h
@@ -1,5 +1,5 @@
 require_extension('D');
 require_fp;
 softfloat_roundingMode = RM;
-WRITE_FRD(ui32_to_f64((uint32_t)RS1));
+WRITE_FRD(ui32_to_f64(sv_reg_uint32(RS1)));
 set_fp_exceptions;
diff --git a/riscv/insns/fcvt_q_w.h b/riscv/insns/fcvt_q_w.h
index fb83f15..1edd319 100644
--- a/riscv/insns/fcvt_q_w.h
+++ b/riscv/insns/fcvt_q_w.h
@@ -1,5 +1,5 @@
 require_extension('Q');
 require_fp;
 softfloat_roundingMode = RM;
-WRITE_FRD(i32_to_f128((int32_t)RS1));
+WRITE_FRD(i32_to_f128(sv_reg_int32(RS1)));
 set_fp_exceptions;
diff --git a/riscv/insns/fcvt_q_wu.h b/riscv/insns/fcvt_q_wu.h
index 7c2ae97..8ec77b3 100644
--- a/riscv/insns/fcvt_q_wu.h
+++ b/riscv/insns/fcvt_q_wu.h
@@ -1,5 +1,5 @@
 require_extension('Q');
 require_fp;
 softfloat_roundingMode = RM;
-WRITE_FRD(ui32_to_f128((uint32_t)RS1));
+WRITE_FRD(ui32_to_f128(sv_reg_uint32(RS1)));
 set_fp_exceptions;
diff --git a/riscv/insns/fcvt_s_w.h b/riscv/insns/fcvt_s_w.h
index 1ddabd8..92af604 100644
--- a/riscv/insns/fcvt_s_w.h
+++ b/riscv/insns/fcvt_s_w.h
@@ -1,5 +1,5 @@
 require_extension('F');
 require_fp;
 softfloat_roundingMode = RM;
-WRITE_FRD(i32_to_f32((int32_t)RS1));
+WRITE_FRD(i32_to_f32(sv_reg_int32(RS1)));
 set_fp_exceptions;