From: Cesar Strauss Date: Sun, 16 Oct 2022 11:52:41 +0000 (-0300) Subject: Move test to expose bug in MultiCompUnit X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=1637a3acdb1959e05e00b645b9ae95c18215651f;p=soc.git Move test to expose bug in MultiCompUnit A bug was discovered in MultiCompUnit, which occurs only when an instruction with zero_a or imm_ok is immediately followed by one with a masked input port. If we move one test out of the way, we get exactly that. --- diff --git a/src/soc/experiment/test/test_compalu_multi.py b/src/soc/experiment/test/test_compalu_multi.py index 4c2e1347..39b24147 100644 --- a/src/soc/experiment/test/test_compalu_multi.py +++ b/src/soc/experiment/test/test_compalu_multi.py @@ -464,13 +464,6 @@ def scoreboard_sim(op): wrmask=[0, 1], src_delays=[2, 0], dest_delays=[1, 0]) - # test combinatorial zero-delay operation - # In the test ALU, any operation other than ADD, MUL, EXTS or SHR - # is zero-delay, and do a subtraction. - # 5 - 2 = 3 - yield from op.issue([5, 2], MicrOp.OP_CMP, [3, 0], - wrmask=[0, 1], - src_delays=[0, 1], dest_delays=[2, 0]) # test all combinations of masked input ports # NOP does not make any request nor response yield from op.issue([5, 2], MicrOp.OP_NOP, [0, 0], @@ -484,6 +477,15 @@ def scoreboard_sim(op): yield from op.issue([2, 0x80], MicrOp.OP_EXTSWSLI, [0xFF80, 0], rdmaskn=[1, 0], wrmask=[0, 1], src_delays=[1, 2], dest_delays=[1, 0]) + + # test combinatorial zero-delay operation + # In the test ALU, any operation other than ADD, MUL, EXTS or SHR + # is zero-delay, and do a subtraction. + # 5 - 2 = 3 + yield from op.issue([5, 2], MicrOp.OP_CMP, [3, 0], + wrmask=[0, 1], + src_delays=[0, 1], dest_delays=[2, 0]) + # test with rc=1, so expect results on the CR output port # 5 + 2 = 7 # 7 > 0 => CR = 0b100