From: Richard Sandiford Date: Tue, 13 Aug 2019 09:49:36 +0000 (+0000) Subject: [AArch64] Add a "y" constraint for V0-V7 X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=163b1f6ab2950553e1cc1b39a6b49293b3390e46;p=gcc.git [AArch64] Add a "y" constraint for V0-V7 Some indexed SVE FCMLA operations have a 3-bit register field that requires one of Z0-Z7. This patch adds a public "y" constraint for that. The patch also documents "x", which is again intended to be a public constraint. 2019-08-13 Richard Sandiford gcc/ * doc/md.texi: Document the x and y constraints for AArch64. * config/aarch64/aarch64.h (FP_LO8_REGNUM_P): New macro. (FP_LO8_REGS): New reg_class. (REG_CLASS_NAMES, REG_CLASS_CONTENTS): Add an entry for FP_LO8_REGS. * config/aarch64/aarch64.c (aarch64_hard_regno_nregs) (aarch64_regno_regclass, aarch64_class_max_nregs): Handle FP_LO8_REGS. * config/aarch64/predicates.md (aarch64_simd_register): Use FP_REGNUM_P instead of checking the classes manually. * config/aarch64/constraints.md (y): New constraint. gcc/testsuite/ * gcc.target/aarch64/asm-x-constraint-1.c: New test. * gcc.target/aarch64/asm-y-constraint-1.c: Likewise. From-SVN: r274367 --- diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 8562f53e678..b3a69bc79c2 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,15 @@ +2019-08-13 Richard Sandiford + + * doc/md.texi: Document the x and y constraints for AArch64. + * config/aarch64/aarch64.h (FP_LO8_REGNUM_P): New macro. + (FP_LO8_REGS): New reg_class. + (REG_CLASS_NAMES, REG_CLASS_CONTENTS): Add an entry for FP_LO8_REGS. + * config/aarch64/aarch64.c (aarch64_hard_regno_nregs) + (aarch64_regno_regclass, aarch64_class_max_nregs): Handle FP_LO8_REGS. + * config/aarch64/predicates.md (aarch64_simd_register): Use + FP_REGNUM_P instead of checking the classes manually. + * config/aarch64/constraints.md (y): New constraint. + 2019-08-13 Richard Sandiford * config/aarch64/iterators.md (perm_insn): Include the "1"/"2" suffix. diff --git a/gcc/config/aarch64/aarch64.c b/gcc/config/aarch64/aarch64.c index 48ec1ac5d5e..6a674a3ff09 100644 --- a/gcc/config/aarch64/aarch64.c +++ b/gcc/config/aarch64/aarch64.c @@ -1610,6 +1610,7 @@ aarch64_hard_regno_nregs (unsigned regno, machine_mode mode) { case FP_REGS: case FP_LO_REGS: + case FP_LO8_REGS: if (aarch64_sve_data_mode_p (mode)) return exact_div (GET_MODE_SIZE (mode), BYTES_PER_SVE_VECTOR).to_constant (); @@ -8279,7 +8280,8 @@ aarch64_regno_regclass (unsigned regno) return POINTER_REGS; if (FP_REGNUM_P (regno)) - return FP_LO_REGNUM_P (regno) ? FP_LO_REGS : FP_REGS; + return (FP_LO8_REGNUM_P (regno) ? FP_LO8_REGS + : FP_LO_REGNUM_P (regno) ? FP_LO_REGS : FP_REGS); if (PR_REGNUM_P (regno)) return PR_LO_REGNUM_P (regno) ? PR_LO_REGS : PR_HI_REGS; @@ -8569,6 +8571,7 @@ aarch64_class_max_nregs (reg_class_t regclass, machine_mode mode) case POINTER_AND_FP_REGS: case FP_REGS: case FP_LO_REGS: + case FP_LO8_REGS: if (aarch64_sve_data_mode_p (mode) && constant_multiple_p (GET_MODE_SIZE (mode), BYTES_PER_SVE_VECTOR, &nregs)) diff --git a/gcc/config/aarch64/aarch64.h b/gcc/config/aarch64/aarch64.h index 34fca9003cc..0c27d90beab 100644 --- a/gcc/config/aarch64/aarch64.h +++ b/gcc/config/aarch64/aarch64.h @@ -563,6 +563,9 @@ extern unsigned aarch64_architecture_version; #define FP_LO_REGNUM_P(REGNO) \ (((unsigned) (REGNO - V0_REGNUM)) <= (V15_REGNUM - V0_REGNUM)) +#define FP_LO8_REGNUM_P(REGNO) \ + (((unsigned) (REGNO - V0_REGNUM)) <= (V7_REGNUM - V0_REGNUM)) + #define PR_REGNUM_P(REGNO)\ (((unsigned) (REGNO - P0_REGNUM)) <= (P15_REGNUM - P0_REGNUM)) @@ -581,6 +584,7 @@ enum reg_class GENERAL_REGS, STACK_REG, POINTER_REGS, + FP_LO8_REGS, FP_LO_REGS, FP_REGS, POINTER_AND_FP_REGS, @@ -600,6 +604,7 @@ enum reg_class "GENERAL_REGS", \ "STACK_REG", \ "POINTER_REGS", \ + "FP_LO8_REGS", \ "FP_LO_REGS", \ "FP_REGS", \ "POINTER_AND_FP_REGS", \ @@ -616,6 +621,7 @@ enum reg_class { 0x7fffffff, 0x00000000, 0x00000003 }, /* GENERAL_REGS */ \ { 0x80000000, 0x00000000, 0x00000000 }, /* STACK_REG */ \ { 0xffffffff, 0x00000000, 0x00000003 }, /* POINTER_REGS */ \ + { 0x00000000, 0x000000ff, 0x00000000 }, /* FP_LO8_REGS */ \ { 0x00000000, 0x0000ffff, 0x00000000 }, /* FP_LO_REGS */ \ { 0x00000000, 0xffffffff, 0x00000000 }, /* FP_REGS */ \ { 0xffffffff, 0xffffffff, 0x00000003 }, /* POINTER_AND_FP_REGS */\ diff --git a/gcc/config/aarch64/constraints.md b/gcc/config/aarch64/constraints.md index 824000a8423..6763d3db129 100644 --- a/gcc/config/aarch64/constraints.md +++ b/gcc/config/aarch64/constraints.md @@ -36,6 +36,9 @@ (define_register_constraint "x" "FP_LO_REGS" "Floating point and SIMD vector registers V0 - V15.") +(define_register_constraint "y" "FP_LO8_REGS" + "Floating point and SIMD vector registers V0 - V7.") + (define_constraint "I" "A constant that can be used with an ADD operation." (and (match_code "const_int") diff --git a/gcc/config/aarch64/predicates.md b/gcc/config/aarch64/predicates.md index 2cd0b87b287..3a8b507cbc7 100644 --- a/gcc/config/aarch64/predicates.md +++ b/gcc/config/aarch64/predicates.md @@ -53,8 +53,7 @@ (define_predicate "aarch64_simd_register" (and (match_code "reg") - (ior (match_test "REGNO_REG_CLASS (REGNO (op)) == FP_LO_REGS") - (match_test "REGNO_REG_CLASS (REGNO (op)) == FP_REGS")))) + (match_test "FP_REGNUM_P (REGNO (op))"))) (define_predicate "aarch64_reg_or_zero" (and (match_code "reg,subreg,const_int,const_double") diff --git a/gcc/doc/md.texi b/gcc/doc/md.texi index af216da6768..7751984bf5f 100644 --- a/gcc/doc/md.texi +++ b/gcc/doc/md.texi @@ -1748,6 +1748,12 @@ The stack pointer register (@code{SP}) @item w Floating point register, Advanced SIMD vector register or SVE vector register +@item x +Like @code{w}, but restricted to registers 0 to 15 inclusive. + +@item y +Like @code{w}, but restricted to registers 0 to 7 inclusive. + @item Upl One of the low eight SVE predicate registers (@code{P0} to @code{P7}) diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog index 9326a92d8a3..e16b2b6b80d 100644 --- a/gcc/testsuite/ChangeLog +++ b/gcc/testsuite/ChangeLog @@ -1,3 +1,8 @@ +2019-08-13 Richard Sandiford + + * gcc.target/aarch64/asm-x-constraint-1.c: New test. + * gcc.target/aarch64/asm-y-constraint-1.c: Likewise. + 2019-08-13 Janne Blomqvist PR fortran/91414 diff --git a/gcc/testsuite/gcc.target/aarch64/asm-x-constraint-1.c b/gcc/testsuite/gcc.target/aarch64/asm-x-constraint-1.c new file mode 100644 index 00000000000..a71043be504 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/asm-x-constraint-1.c @@ -0,0 +1,34 @@ +/* { dg-do compile } */ +/* { dg-options "-O" } */ + +void +f (void) +{ + register float s0 asm ("s0"); + register float s7 asm ("s7"); + register float s8 asm ("s8"); + register float s15 asm ("s15"); + register float s16 asm ("s16"); + register float s31 asm ("s31"); + asm volatile ("// s0 out: %s0" : "=w" (s0)); + asm volatile ("// s0 in: %s0" :: "x" (s0)); + asm volatile ("// s7 out: %s0" : "=w" (s7)); + asm volatile ("// s7 in: %s0" :: "x" (s7)); + asm volatile ("// s8 out: %s0" : "=w" (s8)); + asm volatile ("// s8 in: %s0" :: "x" (s8)); + asm volatile ("// s15 out: %s0" : "=w" (s15)); + asm volatile ("// s15 in: %s0" :: "x" (s15)); + asm volatile ("// s16 out: %s0" : "=w" (s16)); + asm volatile ("// s16 in: %s0" :: "x" (s16)); + asm volatile ("// s31 out: %s0" : "=w" (s31)); + asm volatile ("// s31 in: %s0" :: "x" (s31)); +} + +/* { dg-final { scan-assembler {\t// s0 out: s0\n.*[/]/ s0 in: s0\n} } } */ +/* { dg-final { scan-assembler {\t// s7 out: s7\n.*[/]/ s7 in: s7\n} } } */ +/* { dg-final { scan-assembler {\t// s8 out: s8\n.*[/]/ s8 in: s8\n} } } */ +/* { dg-final { scan-assembler {\t// s15 out: s15\n.*[/]/ s15 in: s15\n} } } */ +/* { dg-final { scan-assembler {\t// s16 out: s16\n.*\tfmov\t(s[0-7]), s16\n.*[/]/ s16 in: \1\n} } } */ +/* { dg-final { scan-assembler {\t// s31 out: s31\n.*\tfmov\t(s[0-7]), s31\n.*[/]/ s31 in: \1\n} } } */ +/* { dg-final { scan-assembler-not {\t// s16 in: s16\n} } } */ +/* { dg-final { scan-assembler-not {\t// s31 in: s31\n} } } */ diff --git a/gcc/testsuite/gcc.target/aarch64/asm-y-constraint-1.c b/gcc/testsuite/gcc.target/aarch64/asm-y-constraint-1.c new file mode 100644 index 00000000000..4a3fcac56b3 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/asm-y-constraint-1.c @@ -0,0 +1,36 @@ +/* { dg-do compile } */ +/* { dg-options "-O" } */ + +void +f (void) +{ + register float s0 asm ("s0"); + register float s7 asm ("s7"); + register float s8 asm ("s8"); + register float s15 asm ("s15"); + register float s16 asm ("s16"); + register float s31 asm ("s31"); + asm volatile ("// s0 out: %s0" : "=w" (s0)); + asm volatile ("// s0 in: %s0" :: "y" (s0)); + asm volatile ("// s7 out: %s0" : "=w" (s7)); + asm volatile ("// s7 in: %s0" :: "y" (s7)); + asm volatile ("// s8 out: %s0" : "=w" (s8)); + asm volatile ("// s8 in: %s0" :: "y" (s8)); + asm volatile ("// s15 out: %s0" : "=w" (s15)); + asm volatile ("// s15 in: %s0" :: "y" (s15)); + asm volatile ("// s16 out: %s0" : "=w" (s16)); + asm volatile ("// s16 in: %s0" :: "y" (s16)); + asm volatile ("// s31 out: %s0" : "=w" (s31)); + asm volatile ("// s31 in: %s0" :: "y" (s31)); +} + +/* { dg-final { scan-assembler {\t// s0 out: s0\n.*[/]/ s0 in: s0\n} } } */ +/* { dg-final { scan-assembler {\t// s7 out: s7\n.*[/]/ s7 in: s7\n} } } */ +/* { dg-final { scan-assembler {\t// s8 out: s8\n.*\tfmov\t(s[0-7]), s8\n.*[/]/ s8 in: \1\n} } } */ +/* { dg-final { scan-assembler {\t// s15 out: s15\n.*\tfmov\t(s[0-7]), s15\n.*[/]/ s15 in: \1\n} } } */ +/* { dg-final { scan-assembler {\t// s16 out: s16\n.*\tfmov\t(s[0-7]), s16\n.*[/]/ s16 in: \1\n} } } */ +/* { dg-final { scan-assembler {\t// s31 out: s31\n.*\tfmov\t(s[0-7]), s31\n.*[/]/ s31 in: \1\n} } } */ +/* { dg-final { scan-assembler-not {\t// s8 in: s8\n} } } */ +/* { dg-final { scan-assembler-not {\t// s15 in: s15\n} } } */ +/* { dg-final { scan-assembler-not {\t// s16 in: s16\n} } } */ +/* { dg-final { scan-assembler-not {\t// s31 in: s31\n} } } */