From: Andreas Krebbel Date: Thu, 7 Nov 2019 11:52:05 +0000 (+0000) Subject: IBM Z: Add pattern for load truth value of comparison into reg X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=163f23d21e5f2faee08163f2dcb363042b53ee1e;p=gcc.git IBM Z: Add pattern for load truth value of comparison into reg The RTXs used to express an overflow condition check in add/sub/mul are too complex for if conversion. However, there is code in noce_emit_store_flag which generates a simple CC compare as the base for using a conditional load. All we have to do is to provide a pattern to store the truth value of a CC compare into a GPR. Done with the attached patch. 2019-11-07 Andreas Krebbel * config/s390/s390.md ("*cstorecc_z13"): New insn_and_split pattern. gcc/testsuite/ChangeLog: 2019-11-07 Andreas Krebbel * gcc.target/s390/addsub-signed-overflow-1.c: Expect lochi instructions to be used. * gcc.target/s390/addsub-signed-overflow-2.c: Likewise. * gcc.target/s390/mul-signed-overflow-1.c: Likewise. * gcc.target/s390/mul-signed-overflow-2.c: Likewise. * gcc.target/s390/vector/vec-scalar-cmp-1.c: Check for 32 and 64 bit variant of lochi. Swap the values for the lochi's. * gcc.target/s390/zvector/vec-cmp-1.c: Likewise. From-SVN: r277922 --- diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 55532cc5236..aba47075c0a 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,8 @@ +2019-11-07 Andreas Krebbel + + * config/s390/s390.md ("*cstorecc_z13"): New insn_and_split + pattern. + 2019-11-07 Richard Biener PR tree-optimization/92405 diff --git a/gcc/config/s390/s390.md b/gcc/config/s390/s390.md index e3881d07f2b..c1d73d5ca42 100644 --- a/gcc/config/s390/s390.md +++ b/gcc/config/s390/s390.md @@ -6810,6 +6810,21 @@ [(set (match_dup 0) (ashiftrt:SI (match_dup 0) (const_int 28))) (clobber (reg:CC CC_REGNUM))])]) +; Such patterns get directly emitted by noce_emit_store_flag. +(define_insn_and_split "*cstorecc_z13" + [(set (match_operand:GPR 0 "register_operand" "=&d") + (match_operator:GPR 1 "s390_comparison" + [(match_operand 2 "cc_reg_operand" "c") + (match_operand 3 "const_int_operand" "")]))] + "TARGET_Z13" + "#" + "reload_completed" + [(set (match_dup 0) (const_int 0)) + (set (match_dup 0) + (if_then_else:GPR + (match_op_dup 1 [(match_dup 2) (match_dup 3)]) + (const_int 1) + (match_dup 0)))]) ;; ;; - Conditional move instructions (introduced with z196) diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog index 07d3a5f1648..b42b78b4d39 100644 --- a/gcc/testsuite/ChangeLog +++ b/gcc/testsuite/ChangeLog @@ -1,3 +1,14 @@ +2019-11-07 Andreas Krebbel + + * gcc.target/s390/addsub-signed-overflow-1.c: Expect lochi + instructions to be used. + * gcc.target/s390/addsub-signed-overflow-2.c: Likewise. + * gcc.target/s390/mul-signed-overflow-1.c: Likewise. + * gcc.target/s390/mul-signed-overflow-2.c: Likewise. + * gcc.target/s390/vector/vec-scalar-cmp-1.c: Check for 32 and 64 + bit variant of lochi. Swap the values for the lochi's. + * gcc.target/s390/zvector/vec-cmp-1.c: Likewise. + 2019-11-07 Martin Jambor PR lto/70929 diff --git a/gcc/testsuite/gcc.target/s390/addsub-signed-overflow-1.c b/gcc/testsuite/gcc.target/s390/addsub-signed-overflow-1.c index 367dbcb3774..143220d5541 100644 --- a/gcc/testsuite/gcc.target/s390/addsub-signed-overflow-1.c +++ b/gcc/testsuite/gcc.target/s390/addsub-signed-overflow-1.c @@ -79,3 +79,5 @@ main () /* { dg-final { scan-assembler-not "\trisbg" { target { lp64 } } } } */ /* Just one for the ret != 6 comparison. */ /* { dg-final { scan-assembler-times "ci" 1 } } */ +/* { dg-final { scan-assembler-times "\tlochio\t" 6 { target { ! lp64 } } } } */ +/* { dg-final { scan-assembler-times "\tlocghio\t" 6 { target lp64 } } } */ diff --git a/gcc/testsuite/gcc.target/s390/addsub-signed-overflow-2.c b/gcc/testsuite/gcc.target/s390/addsub-signed-overflow-2.c index 230ad4af1e7..798e489cece 100644 --- a/gcc/testsuite/gcc.target/s390/addsub-signed-overflow-2.c +++ b/gcc/testsuite/gcc.target/s390/addsub-signed-overflow-2.c @@ -78,3 +78,5 @@ main () /* { dg-final { scan-assembler-not "\trisbg" { target { lp64 } } } } */ /* Just one for the ret != 3 comparison. */ /* { dg-final { scan-assembler-times "ci" 1 } } */ +/* { dg-final { scan-assembler-times "\tlochio\t" 6 { target { ! lp64 } } } } */ +/* { dg-final { scan-assembler-times "\tlocghio\t" 6 { target lp64 } } } */ diff --git a/gcc/testsuite/gcc.target/s390/mul-signed-overflow-1.c b/gcc/testsuite/gcc.target/s390/mul-signed-overflow-1.c index b3db60ffef5..fdf56d6e695 100644 --- a/gcc/testsuite/gcc.target/s390/mul-signed-overflow-1.c +++ b/gcc/testsuite/gcc.target/s390/mul-signed-overflow-1.c @@ -54,3 +54,5 @@ main () /* { dg-final { scan-assembler-not "\trisbg" { target { lp64 } } } } */ /* Just one for the ret != 3 comparison. */ /* { dg-final { scan-assembler-times "ci" 1 } } */ +/* { dg-final { scan-assembler-times "\tlochio\t" 3 { target { ! lp64 } } } } */ +/* { dg-final { scan-assembler-times "\tlocghio\t" 3 { target lp64 } } } */ diff --git a/gcc/testsuite/gcc.target/s390/mul-signed-overflow-2.c b/gcc/testsuite/gcc.target/s390/mul-signed-overflow-2.c index 76b3fa60361..d0088188aa2 100644 --- a/gcc/testsuite/gcc.target/s390/mul-signed-overflow-2.c +++ b/gcc/testsuite/gcc.target/s390/mul-signed-overflow-2.c @@ -54,3 +54,5 @@ main () /* { dg-final { scan-assembler-not "\trisbg" { target { lp64 } } } } */ /* Just one for the ret != 3 comparison. */ /* { dg-final { scan-assembler-times "ci" 1 } } */ +/* { dg-final { scan-assembler-times "\tlochio\t" 3 { target { ! lp64 } } } } */ +/* { dg-final { scan-assembler-times "\tlocghio\t" 3 { target lp64 } } } */ diff --git a/gcc/testsuite/gcc.target/s390/vector/vec-scalar-cmp-1.c b/gcc/testsuite/gcc.target/s390/vector/vec-scalar-cmp-1.c index 073d574aa5e..03db4e0854f 100644 --- a/gcc/testsuite/gcc.target/s390/vector/vec-scalar-cmp-1.c +++ b/gcc/testsuite/gcc.target/s390/vector/vec-scalar-cmp-1.c @@ -12,7 +12,8 @@ eq (double a, double b) return a == b; } -/* { dg-final { scan-assembler "eq:\n\[^:\]*\twfcdb\t%v\[0-9\]*,%v\[0-9\]*\n\t\[^:\]+\tlochine\t%r2,0" } } */ +/* { dg-final { scan-assembler "eq:\n\[^:\]*\twfcdb\t%v\[0-9\]*,%v\[0-9\]*\n\t\[^:\]+\tlochie\t%r2,1" { target { ! lp64 } } } } */ +/* { dg-final { scan-assembler "eq:\n\[^:\]*\twfcdb\t%v\[0-9\]*,%v\[0-9\]*\n\t\[^:\]+\tlocghie\t%r2,1" { target lp64 } } } */ int ne (double a, double b) @@ -23,7 +24,8 @@ ne (double a, double b) return a != b; } -/* { dg-final { scan-assembler "ne:\n\[^:\]*\twfcdb\t%v\[0-9\]*,%v\[0-9\]*\n\t\[^:\]+\tlochie\t%r2,0" } } */ +/* { dg-final { scan-assembler "ne:\n\[^:\]*\twfcdb\t%v\[0-9\]*,%v\[0-9\]*\n\t\[^:\]+\tlochine\t%r2,1" { target { ! lp64 } } } } */ +/* { dg-final { scan-assembler "ne:\n\[^:\]*\twfcdb\t%v\[0-9\]*,%v\[0-9\]*\n\t\[^:\]+\tlocghine\t%r2,1" { target lp64 } } } */ int gt (double a, double b) @@ -34,7 +36,8 @@ gt (double a, double b) return a > b; } -/* { dg-final { scan-assembler "gt:\n\[^:\]*\twfkdb\t%v\[0-9\]*,%v\[0-9\]*\n\t\[^:\]+\tlochinh\t%r2,0" } } */ +/* { dg-final { scan-assembler "gt:\n\[^:\]*\twfkdb\t%v\[0-9\]*,%v\[0-9\]*\n\t\[^:\]+\tlochih\t%r2,1" { target { ! lp64 } } } } */ +/* { dg-final { scan-assembler "gt:\n\[^:\]*\twfkdb\t%v\[0-9\]*,%v\[0-9\]*\n\t\[^:\]+\tlocghih\t%r2,1" { target lp64 } } } */ int ge (double a, double b) @@ -45,7 +48,8 @@ ge (double a, double b) return a >= b; } -/* { dg-final { scan-assembler "ge:\n\[^:\]*\twfkdb\t%v\[0-9\]*,%v\[0-9\]*\n\t\[^:\]+\tlochinhe\t%r2,0" } } */ +/* { dg-final { scan-assembler "ge:\n\[^:\]*\twfkdb\t%v\[0-9\]*,%v\[0-9\]*\n\t\[^:\]+\tlochihe\t%r2,1" { target { ! lp64 } } } } */ +/* { dg-final { scan-assembler "ge:\n\[^:\]*\twfkdb\t%v\[0-9\]*,%v\[0-9\]*\n\t\[^:\]+\tlocghihe\t%r2,1" { target lp64 } } } */ int lt (double a, double b) @@ -56,7 +60,8 @@ lt (double a, double b) return a < b; } -/* { dg-final { scan-assembler "lt:\n\[^:\]*\twfkdb\t%v\[0-9\]*,%v\[0-9\]*\n\t\[^:\]+\tlochinl\t%r2,0" } } */ +/* { dg-final { scan-assembler "lt:\n\[^:\]*\twfkdb\t%v\[0-9\]*,%v\[0-9\]*\n\t\[^:\]+\tlochil\t%r2,1" { target { ! lp64 } } } } */ +/* { dg-final { scan-assembler "lt:\n\[^:\]*\twfkdb\t%v\[0-9\]*,%v\[0-9\]*\n\t\[^:\]+\tlocghil\t%r2,1" { target lp64 } } } */ int le (double a, double b) @@ -67,4 +72,5 @@ le (double a, double b) return a <= b; } -/* { dg-final { scan-assembler "le:\n\[^:\]*\twfkdb\t%v\[0-9\]*,%v\[0-9\]*\n\t\[^:\]+\tlochinle\t%r2,0" } } */ +/* { dg-final { scan-assembler "le:\n\[^:\]*\twfkdb\t%v\[0-9\]*,%v\[0-9\]*\n\t\[^:\]+\tlochile\t%r2,1" { target { ! lp64 } } } } */ +/* { dg-final { scan-assembler "le:\n\[^:\]*\twfkdb\t%v\[0-9\]*,%v\[0-9\]*\n\t\[^:\]+\tlocghile\t%r2,1" { target lp64 } } } */ diff --git a/gcc/testsuite/gcc.target/s390/zvector/vec-cmp-1.c b/gcc/testsuite/gcc.target/s390/zvector/vec-cmp-1.c index 58bc39f238b..7cd6d809ac9 100644 --- a/gcc/testsuite/gcc.target/s390/zvector/vec-cmp-1.c +++ b/gcc/testsuite/gcc.target/s390/zvector/vec-cmp-1.c @@ -8,166 +8,190 @@ all_eq_double (vector double a, vector double b) { return vec_all_eq (a, b); } -/* { dg-final { scan-assembler-times all_eq_double:\n\tvfcedbs\t%v\[0-9\]*,%v24,%v26\n\tlhi\t%r2,1\n\tlochine\t%r2,0 1 } } */ +/* { dg-final { scan-assembler-times all_eq_double:\n\tvfcedbs\t%v\[0-9\]*,%v24,%v26\n\tlhi\t%r2,0\n\tlochie\t%r2,1 1 { target { ! lp64 } } } } */ +/* { dg-final { scan-assembler-times all_eq_double:\n\tvfcedbs\t%v\[0-9\]*,%v24,%v26\n\tlghi\t%r2,0\n\tlocghie\t%r2,1 1 { target lp64 } } } */ int __attribute__((noinline,noclone)) all_ne_double (vector double a, vector double b) { return vec_all_ne (a, b); } -/* { dg-final { scan-assembler-times all_ne_double:\n\tvfcedbs\t%v\[0-9\]*,%v24,%v26\n\tlhi\t%r2,1\n\tlochile\t%r2,0 1 } } */ +/* { dg-final { scan-assembler-times all_ne_double:\n\tvfcedbs\t%v\[0-9\]*,%v24,%v26\n\tlhi\t%r2,0\n\tlochinle\t%r2,1 1 { target { ! lp64 } } } } */ +/* { dg-final { scan-assembler-times all_ne_double:\n\tvfcedbs\t%v\[0-9\]*,%v24,%v26\n\tlghi\t%r2,0\n\tlocghinle\t%r2,1 1 { target lp64 } } } */ int __attribute__((noinline,noclone)) all_gt_double (vector double a, vector double b) { return vec_all_gt (a, b); } -/* { dg-final { scan-assembler-times all_gt_double:\n\tvfchdbs\t%v\[0-9\]*,%v24,%v26\n\tlhi\t%r2,1\n\tlochine\t%r2,0 1 } } */ +/* { dg-final { scan-assembler-times all_gt_double:\n\tvfchdbs\t%v\[0-9\]*,%v24,%v26\n\tlhi\t%r2,0\n\tlochie\t%r2,1 1 { target { ! lp64 } } } } */ +/* { dg-final { scan-assembler-times all_gt_double:\n\tvfchdbs\t%v\[0-9\]*,%v24,%v26\n\tlghi\t%r2,0\n\tlocghie\t%r2,1 1 { target lp64 } } } */ int __attribute__((noinline,noclone)) all_lt_double (vector double a, vector double b) { return vec_all_lt (a, b); } -/* { dg-final { scan-assembler-times all_lt_double:\n\tvfchdbs\t%v\[0-9\]*,%v26,%v24\n\tlhi\t%r2,1\n\tlochine\t%r2,0 1 } } */ +/* { dg-final { scan-assembler-times all_lt_double:\n\tvfchdbs\t%v\[0-9\]*,%v26,%v24\n\tlhi\t%r2,0\n\tlochie\t%r2,1 1 { target { ! lp64 } } } } */ +/* { dg-final { scan-assembler-times all_lt_double:\n\tvfchdbs\t%v\[0-9\]*,%v26,%v24\n\tlghi\t%r2,0\n\tlocghie\t%r2,1 1 { target lp64 } } } */ int __attribute__((noinline,noclone)) all_ge_double (vector double a, vector double b) { return vec_all_ge (a, b); } -/* { dg-final { scan-assembler-times all_ge_double:\n\tvfchedbs\t%v\[0-9\]*,%v24,%v26\n\tlhi\t%r2,1\n\tlochine\t%r2,0 1 } } */ +/* { dg-final { scan-assembler-times all_ge_double:\n\tvfchedbs\t%v\[0-9\]*,%v24,%v26\n\tlhi\t%r2,0\n\tlochie\t%r2,1 1 { target { ! lp64 } } } } */ +/* { dg-final { scan-assembler-times all_ge_double:\n\tvfchedbs\t%v\[0-9\]*,%v24,%v26\n\tlghi\t%r2,0\n\tlocghie\t%r2,1 1 { target lp64 } } } */ int __attribute__((noinline,noclone)) all_le_double (vector double a, vector double b) { return vec_all_le (a, b); } -/* { dg-final { scan-assembler-times all_le_double:\n\tvfchedbs\t%v\[0-9\]*,%v26,%v24\n\tlhi\t%r2,1\n\tlochine\t%r2,0 1 } } */ +/* { dg-final { scan-assembler-times all_le_double:\n\tvfchedbs\t%v\[0-9\]*,%v26,%v24\n\tlhi\t%r2,0\n\tlochie\t%r2,1 1 { target { ! lp64 } } } } */ +/* { dg-final { scan-assembler-times all_le_double:\n\tvfchedbs\t%v\[0-9\]*,%v26,%v24\n\tlghi\t%r2,0\n\tlocghie\t%r2,1 1 { target lp64 } } } */ int __attribute__((noinline,noclone)) any_eq_double (vector double a, vector double b) { return vec_any_eq (a, b); } -/* { dg-final { scan-assembler-times any_eq_double:\n\tvfcedbs\t%v\[0-9\]*,%v24,%v26\n\tlhi\t%r2,1\n\tlochinle\t%r2,0 1 } } */ +/* { dg-final { scan-assembler-times any_eq_double:\n\tvfcedbs\t%v\[0-9\]*,%v24,%v26\n\tlhi\t%r2,0\n\tlochile\t%r2,1 1 { target { ! lp64 } } } } */ +/* { dg-final { scan-assembler-times any_eq_double:\n\tvfcedbs\t%v\[0-9\]*,%v24,%v26\n\tlghi\t%r2,0\n\tlocghile\t%r2,1 1 { target lp64 } } } */ int __attribute__((noinline,noclone)) any_ne_double (vector double a, vector double b) { return vec_any_ne (a, b); } -/* { dg-final { scan-assembler-times any_ne_double:\n\tvfcedbs\t%v\[0-9\]*,%v24,%v26\n\tlhi\t%r2,1\n\tlochie\t%r2,0 1 } } */ +/* { dg-final { scan-assembler-times any_ne_double:\n\tvfcedbs\t%v\[0-9\]*,%v24,%v26\n\tlhi\t%r2,0\n\tlochine\t%r2,1 1 { target { ! lp64 } } } } */ +/* { dg-final { scan-assembler-times any_ne_double:\n\tvfcedbs\t%v\[0-9\]*,%v24,%v26\n\tlghi\t%r2,0\n\tlocghine\t%r2,1 1 { target lp64 } } } */ int __attribute__((noinline,noclone)) any_gt_double (vector double a, vector double b) { return vec_any_gt (a, b); } -/* { dg-final { scan-assembler-times any_gt_double:\n\tvfchdbs\t%v\[0-9\]*,%v24,%v26\n\tlhi\t%r2,1\n\tlochinle\t%r2,0 1 } } */ +/* { dg-final { scan-assembler-times any_gt_double:\n\tvfchdbs\t%v\[0-9\]*,%v24,%v26\n\tlhi\t%r2,0\n\tlochile\t%r2,1 1 { target { ! lp64 } } } } */ +/* { dg-final { scan-assembler-times any_gt_double:\n\tvfchdbs\t%v\[0-9\]*,%v24,%v26\n\tlghi\t%r2,0\n\tlocghile\t%r2,1 1 { target lp64 } } } */ int __attribute__((noinline,noclone)) any_lt_double (vector double a, vector double b) { return vec_any_lt (a, b); } -/* { dg-final { scan-assembler-times any_lt_double:\n\tvfchdbs\t%v\[0-9\]*,%v26,%v24\n\tlhi\t%r2,1\n\tlochinle\t%r2,0 1 } } */ +/* { dg-final { scan-assembler-times any_lt_double:\n\tvfchdbs\t%v\[0-9\]*,%v26,%v24\n\tlhi\t%r2,0\n\tlochile\t%r2,1 1 { target { ! lp64 } } } } */ +/* { dg-final { scan-assembler-times any_lt_double:\n\tvfchdbs\t%v\[0-9\]*,%v26,%v24\n\tlghi\t%r2,0\n\tlocghile\t%r2,1 1 { target lp64 } } } */ int __attribute__((noinline,noclone)) any_ge_double (vector double a, vector double b) { return vec_any_ge (a, b); } -/* { dg-final { scan-assembler-times any_ge_double:\n\tvfchedbs\t%v\[0-9\]*,%v24,%v26\n\tlhi\t%r2,1\n\tlochinle\t%r2,0 1 } } */ +/* { dg-final { scan-assembler-times any_ge_double:\n\tvfchedbs\t%v\[0-9\]*,%v24,%v26\n\tlhi\t%r2,0\n\tlochile\t%r2,1 1 { target { ! lp64 } } } } */ +/* { dg-final { scan-assembler-times any_ge_double:\n\tvfchedbs\t%v\[0-9\]*,%v24,%v26\n\tlghi\t%r2,0\n\tlocghile\t%r2,1 1 { target lp64 } } } */ int __attribute__((noinline,noclone)) any_le_double (vector double a, vector double b) { return vec_any_le (a, b); } -/* { dg-final { scan-assembler-times any_le_double:\n\tvfchedbs\t%v\[0-9\]*,%v26,%v24\n\tlhi\t%r2,1\n\tlochinle\t%r2,0 1 } } */ +/* { dg-final { scan-assembler-times any_le_double:\n\tvfchedbs\t%v\[0-9\]*,%v26,%v24\n\tlhi\t%r2,0\n\tlochile\t%r2,1 1 { target { ! lp64 } } } } */ +/* { dg-final { scan-assembler-times any_le_double:\n\tvfchedbs\t%v\[0-9\]*,%v26,%v24\n\tlghi\t%r2,0\n\tlocghile\t%r2,1 1 { target lp64 } } } */ int __attribute__((noinline,noclone)) all_eq_int (vector int a, vector int b) { return vec_all_eq (a, b); } -/* { dg-final { scan-assembler-times all_eq_int:\n\tvceqfs\t%v\[0-9\]*,%v24,%v26\n\tlhi\t%r2,1\n\tlochine\t%r2,0 1 } } */ +/* { dg-final { scan-assembler-times all_eq_int:\n\tvceqfs\t%v\[0-9\]*,%v24,%v26\n\tlhi\t%r2,0\n\tlochie\t%r2,1 1 { target { ! lp64 } } } } */ +/* { dg-final { scan-assembler-times all_eq_int:\n\tvceqfs\t%v\[0-9\]*,%v24,%v26\n\tlghi\t%r2,0\n\tlocghie\t%r2,1 1 { target lp64 } } } */ int __attribute__((noinline,noclone)) all_ne_int (vector int a, vector int b) { return vec_all_ne (a, b); } -/* { dg-final { scan-assembler-times all_ne_int:\n\tvceqfs\t%v\[0-9\]*,%v24,%v26\n\tlhi\t%r2,1\n\tlochile\t%r2,0 1 } } */ +/* { dg-final { scan-assembler-times all_ne_int:\n\tvceqfs\t%v\[0-9\]*,%v24,%v26\n\tlhi\t%r2,0\n\tlochinle\t%r2,1 1 { target { ! lp64 } } } } */ +/* { dg-final { scan-assembler-times all_ne_int:\n\tvceqfs\t%v\[0-9\]*,%v24,%v26\n\tlghi\t%r2,0\n\tlocghinle\t%r2,1 1 { target lp64 } } } */ int __attribute__((noinline,noclone)) all_gt_int (vector int a, vector int b) { return vec_all_gt (a, b); } -/* { dg-final { scan-assembler-times all_gt_int:\n\tvchfs\t%v\[0-9\]*,%v24,%v26\n\tlhi\t%r2,1\n\tlochine\t%r2,0 1 } } */ +/* { dg-final { scan-assembler-times all_gt_int:\n\tvchfs\t%v\[0-9\]*,%v24,%v26\n\tlhi\t%r2,0\n\tlochie\t%r2,1 1 { target { ! lp64 } } } } */ +/* { dg-final { scan-assembler-times all_gt_int:\n\tvchfs\t%v\[0-9\]*,%v24,%v26\n\tlghi\t%r2,0\n\tlocghie\t%r2,1 1 { target lp64 } } } */ int __attribute__((noinline,noclone)) all_lt_int (vector int a, vector int b) { return vec_all_lt (a, b); } -/* { dg-final { scan-assembler-times all_lt_int:\n\tvchfs\t%v\[0-9\]*,%v26,%v24\n\tlhi\t%r2,1\n\tlochine\t%r2,0 1 } } */ +/* { dg-final { scan-assembler-times all_lt_int:\n\tvchfs\t%v\[0-9\]*,%v26,%v24\n\tlhi\t%r2,0\n\tlochie\t%r2,1 1 { target { ! lp64 } } } } */ +/* { dg-final { scan-assembler-times all_lt_int:\n\tvchfs\t%v\[0-9\]*,%v26,%v24\n\tlghi\t%r2,0\n\tlocghie\t%r2,1 1 { target lp64 } } } */ int __attribute__((noinline,noclone)) all_ge_int (vector int a, vector int b) { return vec_all_ge (a, b); } -/* { dg-final { scan-assembler-times all_ge_int:\n\tvchfs\t%v\[0-9\]*,%v26,%v24\n\tlhi\t%r2,1\n\tlochile\t%r2,0 1 } } */ +/* { dg-final { scan-assembler-times all_ge_int:\n\tvchfs\t%v\[0-9\]*,%v26,%v24\n\tlhi\t%r2,0\n\tlochinle\t%r2,1 1 { target { ! lp64 } } } } */ +/* { dg-final { scan-assembler-times all_ge_int:\n\tvchfs\t%v\[0-9\]*,%v26,%v24\n\tlghi\t%r2,0\n\tlocghinle\t%r2,1 1 { target lp64 } } } */ int __attribute__((noinline,noclone)) all_le_int (vector int a, vector int b) { return vec_all_le (a, b); } -/* { dg-final { scan-assembler-times all_le_int:\n\tvchfs\t%v\[0-9\]*,%v24,%v26\n\tlhi\t%r2,1\n\tlochile\t%r2,0 1 } } */ +/* { dg-final { scan-assembler-times all_le_int:\n\tvchfs\t%v\[0-9\]*,%v24,%v26\n\tlhi\t%r2,0\n\tlochinle\t%r2,1 1 { target { ! lp64 } } } } */ +/* { dg-final { scan-assembler-times all_le_int:\n\tvchfs\t%v\[0-9\]*,%v24,%v26\n\tlghi\t%r2,0\n\tlocghinle\t%r2,1 1 { target lp64 } } } */ int __attribute__((noinline,noclone)) any_eq_int (vector int a, vector int b) { return vec_any_eq (a, b); } -/* { dg-final { scan-assembler-times any_eq_int:\n\tvceqfs\t%v\[0-9\]*,%v24,%v26\n\tlhi\t%r2,1\n\tlochinle\t%r2,0 1 } } */ +/* { dg-final { scan-assembler-times any_eq_int:\n\tvceqfs\t%v\[0-9\]*,%v24,%v26\n\tlhi\t%r2,0\n\tlochile\t%r2,1 1 { target { ! lp64 } } } } */ +/* { dg-final { scan-assembler-times any_eq_int:\n\tvceqfs\t%v\[0-9\]*,%v24,%v26\n\tlghi\t%r2,0\n\tlocghile\t%r2,1 1 { target lp64 } } } */ int __attribute__((noinline,noclone)) any_ne_int (vector int a, vector int b) { return vec_any_ne (a, b); } -/* { dg-final { scan-assembler-times any_ne_int:\n\tvceqfs\t%v\[0-9\]*,%v24,%v26\n\tlhi\t%r2,1\n\tlochie\t%r2,0 1 } } */ +/* { dg-final { scan-assembler-times any_ne_int:\n\tvceqfs\t%v\[0-9\]*,%v24,%v26\n\tlhi\t%r2,0\n\tlochine\t%r2,1 1 { target { ! lp64 } } } } */ +/* { dg-final { scan-assembler-times any_ne_int:\n\tvceqfs\t%v\[0-9\]*,%v24,%v26\n\tlghi\t%r2,0\n\tlocghine\t%r2,1 1 { target lp64 } } } */ int __attribute__((noinline,noclone)) any_gt_int (vector int a, vector int b) { return vec_any_gt (a, b); } -/* { dg-final { scan-assembler-times any_gt_int:\n\tvchfs\t%v\[0-9\]*,%v24,%v26\n\tlhi\t%r2,1\n\tlochinle\t%r2,0 1 } } */ +/* { dg-final { scan-assembler-times any_gt_int:\n\tvchfs\t%v\[0-9\]*,%v24,%v26\n\tlhi\t%r2,0\n\tlochile\t%r2,1 1 { target { ! lp64 } } } } */ +/* { dg-final { scan-assembler-times any_gt_int:\n\tvchfs\t%v\[0-9\]*,%v24,%v26\n\tlghi\t%r2,0\n\tlocghile\t%r2,1 1 { target lp64 } } } */ int __attribute__((noinline,noclone)) any_lt_int (vector int a, vector int b) { return vec_any_lt (a, b); } -/* { dg-final { scan-assembler-times any_lt_int:\n\tvchfs\t%v\[0-9\]*,%v26,%v24\n\tlhi\t%r2,1\n\tlochinle\t%r2,0 1 } } */ +/* { dg-final { scan-assembler-times any_lt_int:\n\tvchfs\t%v\[0-9\]*,%v26,%v24\n\tlhi\t%r2,0\n\tlochile\t%r2,1 1 { target { ! lp64 } } } } */ +/* { dg-final { scan-assembler-times any_lt_int:\n\tvchfs\t%v\[0-9\]*,%v26,%v24\n\tlghi\t%r2,0\n\tlocghile\t%r2,1 1 { target lp64 } } } */ int __attribute__((noinline,noclone)) any_ge_int (vector int a, vector int b) { return vec_any_ge (a, b); } -/* { dg-final { scan-assembler-times any_ge_int:\n\tvchfs\t%v\[0-9\]*,%v26,%v24\n\tlhi\t%r2,1\n\tlochie\t%r2,0 1 } } */ +/* { dg-final { scan-assembler-times any_ge_int:\n\tvchfs\t%v\[0-9\]*,%v26,%v24\n\tlhi\t%r2,0\n\tlochine\t%r2,1 1 { target { ! lp64 } } } } */ +/* { dg-final { scan-assembler-times any_ge_int:\n\tvchfs\t%v\[0-9\]*,%v26,%v24\n\tlghi\t%r2,0\n\tlocghine\t%r2,1 1 { target lp64 } } } */ int __attribute__((noinline,noclone)) any_le_int (vector int a, vector int b) { return vec_any_le (a, b); } -/* { dg-final { scan-assembler-times any_le_int:\n\tvchfs\t%v\[0-9\]*,%v24,%v26\n\tlhi\t%r2,1\n\tlochie\t%r2,0 1 } } */ +/* { dg-final { scan-assembler-times any_le_int:\n\tvchfs\t%v\[0-9\]*,%v24,%v26\n\tlhi\t%r2,0\n\tlochine\t%r2,1 1 { target { ! lp64 } } } } */ +/* { dg-final { scan-assembler-times any_le_int:\n\tvchfs\t%v\[0-9\]*,%v24,%v26\n\tlghi\t%r2,0\n\tlocghine\t%r2,1 1 { target lp64 } } } */